National Semiconductor Corporation

Kendin Communications

Other

Hai T Nguyen

Vuong Le

Menping Chang

Sushma Chandrasekaran

Yu-Sheng Yang

Yu-Sheng (Stephen) Yang

The present invention prevents the DLL from locking into the wrong phase, harmonic lock and hang. The detection is independent of temperature, voltage and process that the DLL is running. Including these mechanisms in the DLL design, the operating frequency range of the DLL can be extended significantly. Also many design blocks in the main loop can be reused for these additional circuitries, the design time of this DLL is much faster than to design a whole new hang or harmonic lock prevention circuitries.

Delay locked loop with harmonic lock and hang prevention architecture

An adaptive equalizer system and method uses an averaging algorithm to adjust equalization and amplitude for a data signal. Two sampled data points, spanning a sampling window, are obtained from the equalized signal. The data points are evaluated to determine when a signal condition persists long enough to require equalization adjustment, as well as evaluating persistent conditions in the amplitude of the received data signal. By monitoring persistent conditions in the equalized signal, the average signal received by the equalizer is compensated. The bit resolution of the equalizer control and the amplitude control can be selected for a desired resolution in a system. The incoming data signal is used to generate the requisite timing signals for sampling and control such that high frequency clock circuits and PLL techniques are unnecessary resulting in lower power consumption and reduced costs.

Apparatus and averaging method for equalizing signals

An input signal with an associated pulse width can be sampled using a sampling method that does not require a clock signal. The input signal is compared to a reference level signal to produce a comparator output signal. Strobe signals are generated from the input signal, where the strobe signals occur within a pulse width of the input signal. Sampled data points are generated in response to the comparator output signal and the strobe signals such that the sampled data points are within the pulse-width of the input signal. One of the strobe signals may be used to periodically reset the comparator. The sampling logic circuit may be constructed from common logic gates and memory circuits such as flip-flops. In one example application the sampling method is applied to an equalizer system. The equalizer system includes an equalizer circuit that produces an equalized signal. A data slicer circuit converts the equalized signal into a digital representation. The sampling method is applied to the output of the data slicer circuit to generate the sampled data points in the equalizer system. The sampled data points may be used in the equalizer system or any other system that requires samples of the input signal without the use of a clock signal. Since the sampling system uses the incoming data signal to generate the requisite timing signals for sampling, high frequency clock circuits and phase locked loop techniques are unnecessary resulting in lower power consumption and reduced costs.

Method and apparatus not requiring a clock signal for sampling an input signal

An apparatus for tracking a peak level of an input signal includes a comparator for comparing the peak level of the input signal with a reference peak voltage signal. A sample and block circuit is coupled to the output of the comparator and is capable of sampling a portion of the input signal. The sampled portion of the input signal is defined by a smart window (timing window) which is received by the sample and block circuit. The sample and block circuit controls a charge pump that determines the level of the reference peak voltage signal. A method of generating a reference peak voltage signal includes receiving an input data, generating a timing window based upon the input data to define a sampling portion in the input data, comparing a level of the reference peak voltage signal with a level of the sampling portion in the input data, and determining a level of the reference peak voltage signal based upon the comparing step.

Selective sampled peak detector and method

An apparatus of compensating for offset in a received signal generated from a forward path stage, includes a first peak detector for receiving a first signal from the forward path stage and capable of detecting a peak of the first signal; a second peak detector for receiving a second signal from the forward path stage and capable of detecting a peak of the second signal; a differential amplifier coupled to the first peak detector and the second peak detector and capable of generating an offset control signal; and a compensation stage coupled to the differential amplifier and capable of compensating for offset in the received signal in response to the offset control signal. A method of compensating for offset in a received signal includes detecting a level of a first signal from a forward path stage; detecting a level of a second signal from the forward path stage; and generating an offset control signal to reduce an offset in the received signal in response to the level difference of the first signal and the second signal.

Baseline wander compensation circuit and method

A low power differential receiver input stage using n-channel/p-channel transistor pairs to adjust the voltage levels of differential output signals. A first n-channel/p-channel transistor pair is connected to a first output terminal and a second n-channel/p-channel transistor pair is connected to a second output terminal. First and second differential signals respectively applied to first and second input terminals are passed to the first and second output terminals through first and second resistors, respectively. The first differential signal is applied to the gates of the second n-channel/p-channel transistor pair, thereby adjusting the voltage level at the second output terminal. Similarly, the second differential signal is applied to the gates of the first n-channel/p-channel transistor pair, thereby adjusting the voltage level at the first output terminal.

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San Jose, CA, United States of America

Hai T Nguyen