Semiconductor Manufacturing International (shanghai) Corporation

Ningbo Semiconductor International Corporation

Other

International Business Machines Corporation

Carl Zeiss Microscopy Gmbh

Lenovo (singapore) Pte. Ltd.

Semiconductor Manufacturing International (beijing) Corporation

Carl Zeiss Meditec Ag

Datang Nxp Semiconductors Co., Ltd.

State Grid Shanghai Municipal Electric Power Company

Hai Long Li

Wei Zhang

Wei Wang

Yi Zhang

Ji Guang Zhu

Herb He Huang

Clifford Ian Drowley

Liu Wang

Fei Dong

Shu Gong

Yin Peng Lv

Jinpeng Liu

Wei Huang

Sumeet Kochar

Xiang Li

Martin Stohr

Ilka Schlesiger

Michael Winterot

Hong Qing Zhou

Jie Zhou

Chao Xu

Ting Ye

Qiang Xu

Zhi Xu

Mei Wang

Zhiwei Lin

Zhongyu Li

Jianwei Shu

Yujuan Shen

He He

Jingjing Zhou

Quanrong Gong

Zhe Song

Ralph Aschenbach

Xiaodi Wang

Junchen Zhu

Guangmei Wu

Zhongxiang Liang

Libing Song

Zhong Xiang Liang

Yongjie Zhao

Johnny Li

Yunjie Zhou

Tianyu Qian

Pingping Xu

Jialiang Yuan

Shenfu Zhang

Haowen Zhao

Geng Xian Gu

Yuechao Chen

Jiamin Xu

Pingyu Wang

Chunhui Li

Xiaoxuan Sun

Qi Yuan

The disclosure provides a battery management device, method, and a chip. The device includes: an analog-digital converter connected with a first power supply access terminal, a second power supply access terminal and an impedance measuring element: wherein the analog-digital converter is configured to achieve analog-digital conversion between an accessed power supply and the impedance measuring element; the impedance measuring element is further connected with a comparator and a driving element; the impedance measuring element is configured to test an impedance of the accessed power supply; the comparator is configured to compensate delay generated by the driving element and an excitation signal generator; and the driving element is configured to drive the battery management device to work; and the excitation signal generator is connected with the comparator, the driving element, the first power supply access terminal and the second power supply access terminal.

Battery management device, method and chip

A method for forming a semiconductor device includes forming a first insulator layer on a first substrate of a first semiconductor material, implanting hydrogen ions into the first substrate to form a hydrogen-implanted layer, forming a recessed region in the first substrate, forming a second semiconductor material in the recessed region, and forming a second insulator layer over the second semiconductor material and the first substrate. The method also includes providing a second substrate with a third insulator layer disposed thereon, bonding the first substrate with the second substrate, and removing a lower portion of the first substrate at the hydrogen-implanted layer. A portion of the first substrate is removed to expose a surface of the second semiconductor material in the recessed region, thereby providing a layer of the first semiconductor material adjacent to a layer of the second semiconductor material on the second insulator layer.

Substrate having two semiconductor materials on insulator

A device for preventing cables against external damage based on sound source localization comprises a power supply unit, and a sound source sensor unit, a camera unit, a signal processing unit and a wireless communication unit which are electrically connected to the power supply unit. The signal processing unit is connected to the sound source sensor unit, the camera unit and the wireless communication unit. The camera unit is associated with the sound source sensor unit. When the sound source sensor unit recognizes a target signal, the signal processing unit sends a trigger signal to the camera unit, and then the camera unit is triggered to replay a surveillance video to determine whether or not a target really exists. Compared with the prior art, the device has the advantages of being good in safety, high in reliability and the like.

Device for preventing cables against external damage based on sound source localization

A method for fabricating a semiconductor structure includes providing a wafer and a carrier wafer. The wafer includes a first bonding surface and a plurality of radio-frequency (RF) devices and the carrier wafer includes a second bonding surface. The method further includes performing a surface treatment process on the second bonding surface to convert a surface portion of the carrier wafer into a barrier layer to suppress movement of induced electrical charges in the carrier wafer, and then bonding the wafer with the carrier wafer through the first bonding surface and the second bonding surface, respectively.

Semiconductor structures with improved bonding and fabrication methods thereof

A semiconductor device may include the following elements: a first substrate; a second substrate; a dielectric layer, which may be positioned between the first substrate and the second substrate and may have a hole; a first conductive member, which may be positioned in the dielectric layer; a second conductive member, which may be positioned in the dielectric layer, may be spaced from the first conductive member, and may be positioned closer to the second substrate than the first conductive member; and a third conductive member, which may contact both the first conductive member and the second conductive member through the hole.

Semiconductor device, related manufacturing method, and related electronic device

A method for manufacturing an interconnect structure includes providing a substrate structure including a substrate and a dielectric layer on the substrate, the dielectric layer having an opening extending to the substrate. The method further includes forming a mask layer on at least one portion of the dielectric layer, forming a metal layer filling the opening and covering portions of dielectric layer not covered by the mask layer, removing the mask layer, and planarizing the metal layer so that an upper surface of a remaining portion of the metal layer is flush with an upper surface of the dielectric layer. The method can mitigate the warping problems of the substrate associated with the fabrication of the interconnect structure.

Method of forming interconnect structure with partial copper plating

A test apparatus and a test method for testing a plurality of blocks in a circuit, the plurality of blocks having identical structures. The test apparatus includes a comparing device, configured to collect output responses generated by the plurality of blocks by applying an excitation signal to the plurality of blocks in parallel, compare the output responses of the plurality of blocks to determine whether the output responses of the plurality of blocks are identical, and output results of the comparison of the comparing device; and a determining device, configured to receive the results of the comparison of the comparing device, and determine whether the plurality of blocks have a defect according to the results of the comparison of the comparing device.

Test method and test apparatus for testing a plurality of blocks in a circuit

The present disclosure provides a method for forming a transistor, including: forming a base structure, containing a first gate structure, an active layer covering the first gate structure, and an insulating structure in the active layer; forming a second gate structure on the active layer; forming a source-drain region, including a source region and a drain region in the active layer each on a different side of the second gate structure; and forming a first interlayer dielectric layer covering the base structure and the second gate structure. The method also includes: forming a first contact hole that exposes the first gate structure by etching the first interlayer dielectric layer and the insulating structure; and forming a second contact hole that exposes the second gate structure and a third contact hole that exposes the drain region by etching the first interlayer dielectric layer.

Transistor and method for forming the same

Mount for a medical instrument

The proposed invention involves the use of new drugs with the recombinant soluble tumor necrosis &#x3b1; receptor (HusTNFR) and belongs to the gene engineering technology and gene function application field. This invention uses type I or type II long-acting HusTNFR (LHusTNFR) to perform an intervention for severe liver injury in rats with chronic liver disease using 5 types of animal models. The results showed that LHusTNFR, which has a half-life of 12-140 hours, shows excellent efficacy for preventing the development of severe liver injury on chronic liver disease and for treating early-stage severe liver injury on chronic liver disease. It also significantly reduced the mortality of the model animals. Its efficacy for the prevention and treatment of early-stage severe liver injury on chronic liver disease was significantly better than that of non-LHusTNFR.

Method for decreasing mortality associated with chronic liver disease by use of long-acting human recombinant soluble tumor necrosis factor &#x3b1; receptor

Microscope

Disclosed are a test apparatus and a test method for testing a plurality of blocks in a circuit, the plurality of blocks having identical structures. The test apparatus comprises: a comparing device, configured to collect output responses generated by the plurality of blocks by applying an excitation signal to the plurality of blocks in parallel, compare the output responses of the plurality of blocks to determine whether the output responses of the plurality of blocks are identical, and output results of the comparison of the comparing device; and a determining device, configured to receive the results of the comparison of the comparing device, and determine whether the plurality of blocks have a defect according to the results of the comparison of the comparing device. With the test apparatus and the test method, a process for testing the plurality of blocks having the identical structures may be simplified, and test efficiency may be improved.

Growing community of inventors

Beijing, China

Hai Long Li