Nan Ya Technology Corporation

Hai-Han Hung

Shian-Jyh Lin

Ya-Chih Wang

Shin-Yu Nieh

Shing-Yih Shih

Chung-Yen Chou

Chung-Yuan Lee

Tieh-Chiang Wu

Wei-Ming Liao

Te-Yin Chen

Wen-Chieh Wang

Chien-Mao Liao

Chien-An Yu

Jei-Cheng Huang

Wei-Cheng Shiu

Hsiu-Chun Lee

Teng-Wang Huang

Yu-Wei Liang

Pei-Chi Wu

The invention provides a method for fabricating a semiconductor device, including: forming a dummy gate on a substrate, forming an inter-layer dielectric layer (ILD) on the dummy gate and the substrate, forming a metal layer on the upper surface of the dummy gate, removing the dummy gate to form a trench in the inter-layer dielectric layer (ILD), conformally forming a gate dielectric layer in the trench, conformally forming a first conductive type metal layer on the gate dielectric layer, anisotropic etching the first conductive type metal layer and the gate dielectric layer over the metal layer to form a gap in the inter-layer dielectric layer (ILD), and filling a second conductive type metal layer in the gap.

Method of manufacturing a PMOS transistor comprising a dual work function metal gate

A method for fabricating a semiconductor device is provided. A first polysilicon layer of a first conductivity type is provided on a substrate having first and second active regions. An ion implantation process is performed in the polysilicon layer corresponding to the second active region by using a dopant of a second conductivity type opposite to the first conductivity type, and silane plasma is introduced during the ion implantation process to form a second polysilicon layer thereon and convert the first conductivity type of the first polysilicon layer corresponding to the second active region to the second conductivity type. The first and second polysilicon layers are patterned to form a first gate layer corresponding to the first active region and a second gate layer corresponding to the second active region. A semiconductor device is also provided.

Semiconductor device and fabrication method therof

A hard mask spacer structure includes a first spacer on a device layer, the first spacer defining a plurality of hole patterns and at least an asteriated hole pattern between the hole patterns; and a second spacer on the first spacer and inlaid into the asteriated hole pattern, thereby rounding the asteriated hole pattern.

Hard mask spacer structure and fabrication method thereof

A patterning method has a mask layer and undoped patterns sequentially formed on a target layer. A doping process is performed to surfaces of the undoped patterns to form doped patterns from the surfaces of the undoped patterns. A material is filled in the gaps between the doped patterns. A portion of the doped patterns are then removed to expose the top surfaces of the remaining undoped patterns. The material and the exposed undoped patterns are removed. A portion of the mask layer is removed using the remaining doped patterns as a mask to form a first pattern on the mask layer. A portion of the target layer is removed using the mask layer having the first pattern thereon as a mask so as to form on the target layer a second pattern complementary to the first pattern.

Patterning method

A method of fabricating a semiconductor device having a recess channel structure is provided. A first recess is formed in a substrate. A liner and a filling layer are formed in the first recess. A portion of the substrate adjacent to the first recess and a portion of the liner and the filling layer are removed to form trenches. An insulation layer fills the trenches to form isolation structures. The filling layer is removed, using the liner as an etching stop layer, to expose the insulation layer. A portion of the exposed insulation layer is removed to form a second recess having divots adjacent to the sidewalls of the substrate. The liner is removed. A dielectric layer and a gate are formed over the substrate covering the second recess. Source and drain regions are formed in the substrate adjacent to the second recess.

Method of fabricating semiconductor device having a recess channel structure therein

The invention provides a method for forming a deep trench in a substrate. A sacrificial layer and a liner layer are first used to define the deep trench pattern. The sacrificial layer is then replaced with a silicon glass layer. A thick mask layer includes the silicon glass layer, the liner layer and a silicon nitride layer is formed on the substrate. Through an opening of the thick mask layer, a deep trench is etched into the substrate.

Method for fabricating a deep trench in a substrate

A method of forming a silicon nitride layer. The method comprises providing a substrate having a silicon surface thereon, performing an ion implant process on the silicon surface, implanting nitrogen atoms into the silicon surface, and performing a thermal nitridation process and forming a silicon nitride layer on the substrate, wherein the silicon nitride layer comprises the silicon nitride formed on the silicon surface by reaction of the silicon surface with the nitrogen atoms contained therein.

Method for forming a silicon nitride layer

A method of treating the surface of a deep trench is disclosed. After forming a deep trench in a silicon substrate, the silicon substrate near the surfaces of the deep trench is treated to become amorphous. An annealing process is executed to make the amorphous silicon layer recrystallize into its original lattice arrangement, so as to reduce lattice defects in the surface of the deep trench.

Growing community of inventors

Taoyuan County, Taiwan

Hai-Han Hung