Taiwan Semiconductor Manufacturing Comp. Ltd.

Parabellum Strategic Opportunities Fund LLC

Haynes and Boone, LLP

Hai-Ching Chen

Tien-I Bao

Hsin-Yen Huang

Shau-Lin Shue

Chung-Te Lin

Shao-Kuan Lee

Cheng-Chin Lee

Chi-Lin Teng

Yu-Ming Lin

Ying-Hao Kuo

Rainer Yen-Chieh Huang

Kai-Fang Cheng

Chen-Hua Douglas Yu

Yen-Chieh Huang

Bo-Jiun Lin

Po-Ting Lin

Song-Fu Liao

Chung-Ju Lee

Chun-Hao Tseng

Wan-Yu Lee

Yung-Hsu Wu

Wu-Wei Tsai

Hsiang-Huan Lee

Jung-Hsun Tsai

Sai-Hooi Yeong

Jui Hsieh Lai

Ting-Ya Lo

Ming-Han Lee

Chien-Hua Huang

Ching-Yu Chang

Chia-Tien Wu

Tai-I Yang

Chih Wei Lu

Cheng-Hsiung Tsai

Yu-Sheng Chang

Ching-Yu Lo

Ru-Gun Liu

Tsai-Sheng Gau

Ming-Feng Shieh

Shin-Yi Yang

Chun-Chieh Lu

Hsin-Chieh Yao

Hsiang-Wei Liu

Kuo-Chang Chiang

Chung-En Kao

Yu-Chen Chan

Wen-Cheng Yang

Tung-Ching Tseng

Wen-Chih Chiou

Chia-Hao Chang

Cheng-Chi Chuang

Lin-Yu Huang

Hsin-Ping Chen

Hung-Jung Tu

Keith Kuang-Kuo Koai

Yu-Chieh Liao

Ming Han Lee

Jay Lai

Kai-Wen Cheng

Ming-Shih Yeh

Wei-Chih Wen

Henry Lo

Shih-Kang Fu

Sai-hooi Yeong

Sunil Kumar Singh

Yu-Chuan Shih

Yu-Ming Hsiang

Yan-Yi Chen

Tien-l Bao

Kuang-Kuo Koai

Kai-Feng Cheng

Harold C H Hsiung

A semiconductor device includes a first conductive feature, a second conductive feature, and a first dielectric layer positioned between the first conductive feature and the second conductive feature. An etch stop layer is over the first dielectric layer. A cap layer is over the first conductive feature, the second conductive feature, and the etch stop layer.

Method of forming semiconductor device comprising conductive feature, dielectric layer adjacent conductive feature, and etch stop layer on top surface of dielectric layer

An interconnect structure is provided. The interconnect structure includes a first metal line and a second metal line in a first dielectric layer, a catalyst layer on the first dielectric layer, a dielectric block on the catalyst layer, an etching stop layer along the second metal line, the catalyst layer and the dielectric block, a second dielectric layer over the etching stop layer, and a first via through the second dielectric layer and the etching stop layer on the first metal line. A first interface between the etching stop layer and the second metal line is level to a second interface between the catalyst layer and the first dielectric layer.

Interconnect structure and method for forming the same

Ferroelectric devices, including FeFET and/or FeRAM devices, include ferroelectric material layers deposited using atomic layer deposition (ALD). By controlling parameters of the ALD deposition sequence, the crystal structure and ferroelectric properties of the ferroelectric layer may be engineered. An ALD deposition sequence including relatively shorter precursor pulse durations and purge durations between successive precursor pulses may provide a ferroelectric layer having relatively uniform crystal grain sizes and a small mean grain size (e.g., ≤3 nm), which may provide effective ferroelectric performance. An ALD deposition sequence including relatively longer precursor pulse durations and purge durations between successive precursor pulses may provide a ferroelectric layer having less uniform crystal grain sizes and a larger mean grain size (e.g., ≥7 nm). Ferroelectric layers having larger mean grain sizes may exhibit enhanced crystallinity and a stabilized orthorhombic crystal phase, particularly in relatively thin layers (e.g., ≤15 nm in thickness).

Ferroelectric memory devices having improved ferroelectric properties and methods of making the same

In some embodiments, the present disclosure relates to a device that includes an active layer, a gate electrode, a passivation structure, a source contact, and a drain contact arranged over a substrate. The gate electrode is arranged over the substrate and is spaced apart from the active layer by a gate dielectric layer. The passivation structure is arranged over the active layer. The source contact extends through the passivation structure and contacts the active layer. The drain contact extends through the passivation structure and contacts the active layer. The passivation structure is hydrophobic.

Passivation structure for a thin film transistor

A thin film transistor includes an active layer and at least one gate stack. The active layer may be formed using multiple iterations of a unit layer stack deposition process, which includes an acceptor-type oxide deposition process and a post-transition metal oxide deposition process. A surface of each gate dielectric within the at least one gate stack contacts a surface of a respective layer of the oxide of the acceptor-type element so that leakage current of the active layer may be minimized. A source electrode and a drain electrode may contact an oxide layer providing lower contact resistance such as a layer of the post-transition metal oxide or a zinc oxide layer within the active layer.

Thin film transistor including a compositionally-modulated active region and methods for forming the same

In one embodiment, a self-aligned via is presented. In one embodiment, an inhibitor layer is selectively deposited on the lower conductive region. In one embodiment, a dielectric is selectively deposited on the lower conductive region. In one embodiment, the deposited dielectric may be selectively etched. In one embodiment, an inhibitor is selectively deposited on the lower dielectric region. In one embodiment, a dielectric is selectively deposited on the lower dielectric region. In one embodiment, the deposited dielectric over the lower conductive region has a different etch rate than the deposited dielectric over the lower dielectric region which may lead to a via structure that is aligned with the lower conductive region.

Self-align via structure by selective deposition

Provided are a ferroelectric memory device and a method of forming the same. The ferroelectric memory device includes: a gate electrode; a ferroelectric layer, disposed on the gate electrode; a channel layer, disposed on the ferroelectric layer; a pair of source/drain (S/D) electrodes, disposed on the channel layer; a first insertion layer, disposed between the gate electrode and the ferroelectric layer; and a second insertion layer, disposed between the ferroelectric layer and the channel layer, wherein the second insertion layer has a thickness less than a thickness of the first insertion layer.

Ferroelectric memory device and method of forming the same

A thin film transistor may be manufactured by forming a gate electrode in an insulating layer over a substrate, forming a gate dielectric over the gate electrode and the insulating layer, forming an active layer over the gate electrode, and forming a source electrode and a drain electrode contacting a respective portion of a top surface of the active layer. A surface oxygen concentration may be increased in at least one of the gate dielectric and the active layer by introducing oxygen atoms into a surface region of a respective one of the gate dielectric and the active layer.

Thin film transistor including a compositionally- graded gate dielectric and methods for forming the same

In some embodiments, the present disclosure relates to a 3D memory device, including a plurality of gate lines interleaved between a plurality of dielectric layers in a vertical direction, the plurality of gate lines forming recesses between the plurality of dielectric layers; a source/drain line disposed next to the plurality of dielectric layers, spaced from the plurality of gate lines by the recesses in a lateral direction; a ferroelectric film arranged laterally between sidewalls of the plurality of gate lines and the source/drain line and confined within the recesses; and a semiconductor film disposed within the recesses and spacing the ferroelectric film from the source/drain line.

3D lateral patterning via selective deposition for ferroelectric devices

An integrated chip including a semiconductor layer over a substrate. A pair of source/drains are arranged along the semiconductor layer. A first metal layer is over the substrate. A second metal layer is over the first metal layer. A ferroelectric layer is over the second metal layer. The first metal layer has a first crystal orientation and the second metal layer has a second crystal orientation different from the first crystal orientation.

Ferroelectric memory device with a metal layer having a crystal orientation for improving ferroelectric polarization and method for forming the ferroelectric memory device

In some embodiments, the present disclosure relates to an integrated chip that includes a first conductive structure arranged over a substrate. A memory layer is arranged over the first conductive structure, below a second conductive structure, and includes a ferroelectric material. An annealed seed layer is arranged between the first and second conductive structures and directly on a first side of the memory layer. An amount of the crystal structure that includes an orthorhombic phase is greater than about 35 percent.

Annealed seed layer to improve ferroelectric properties of memory layer

A method and structure for forming a barrier-free interconnect layer includes patterning a metal layer disposed over a substrate to form a patterned metal layer including one or more trenches. In some embodiments, the method further includes selectively depositing a barrier layer on metal surfaces of the patterned metal layer within the one or more trenches. In some examples, and after selectively depositing the barrier layer, a dielectric layer is deposited within the one or more trenches. Thereafter, the selectively deposited barrier layer may be removed to form air gaps between the patterned metal layer and the dielectric layer.

Interconnect structures including air gaps

A method of forming a semiconductor device includes providing a precursor. The precursor includes a substrate; a gate stack over the substrate; a first dielectric layer over the gate stack; a gate spacer on sidewalls of the gate stack and on sidewalls of the first dielectric layer; and source and drain (S/D) contacts on opposing sides of the gate stack. The method further includes recessing the gate spacer to at least partially expose the sidewalls of the first dielectric layer but not to expose the sidewalls of the gate stack. The method further includes forming a spacer protection layer over the gate spacer, the first dielectric layer, and the S/D contacts.

Method and structure for semiconductor device having gate spacer protection layer

The present disclosure involves forming a porous low-k dielectric structure. A plurality of conductive elements is formed over the substrate. The conductive elements are separated from one another by a plurality of openings. A barrier layer is formed over the conductive elements. The barrier layer is formed to cover sidewalls of the openings. A treatment process is performed to the barrier layer. The barrier layer becomes hydrophilic after the treatment process is performed. A dielectric material is formed over the barrier layer after the treatment process has been performed. The dielectric material fills the openings and contains a plurality of porogens.

System and method of forming a porous low-k structure

A method of fabricating a transistor structure is provided. The method comprises forming a gate electrode in a dielectric layer of an interconnect structure; forming a monolayer on a portion of the dielectric layer laterally spaced from the gate electrode; sequentially forming a ferroelectric layer, a barrier layer and a channel layer on the gate electrode; and forming a source/drain electrode on the channel layer.

Method of fabricating transistor structure

Growing community of inventors

Hsinchu, Taiwan

Hai-Ching Chen