Marvell Israel (misl) Ltd.

Marvell International Limited

Marvell Semiconductor Israel Ltd.

Haggai Telem

Randall Don Briggs

David Moshe

William B Weiser

Michael Weiner

Walter Lee McNall

Eran Maor

Gidon Bratman

Hagai Yoeli

Ohad Glazer

An integrated circuit has operational circuitry to perform an operation. An operational regulator regulates an operating condition of the operational circuitry. The operational regulator has a sample clock to generate a sample clock signal. The sample clock signal correlates to a manufacturing variation of the electronic circuitry. The operational regulator also includes a configurator to evaluate the sample clock signal and generate a configuration signal according to the evaluation. A controller is provided to receive the configuration signal and control an operating condition of the operational circuitry according to the configuration signal.

Regulating an operating condition of an integrated circuit to compensate for a manufacturing variation

An approach for producing optimized integrated circuit designs that support sequential flow partial scan testing may be embedded within an integrated circuit electronic design device. Using the approach, an integrated circuit design may be analyzed to identify and remove scan-enabled memory elements, or scan elements, that are redundant. The redundant scan elements may be replaced with memory elements that do not support scan testing. Once the redundant scan elements are removed, the integrated circuit design my be optimized using automated techniques to reduce the area of the integrated circuit physical layout and to simplify/minimize routing connections between remaining features within the integrated circuit design. The described approach may achieve a reduced total area layout and complexity, an improved time/frequency response, and/or reduced power consumption and/or heat generation within the circuit design, without reducing the fault coverage achieve during testing.

Method and apparatus for identifying redundant scan elements

A circuit generates a qualified data read strobe signal from a start burst signal and a bidirectional data strobe signal in a DDR memory control module. The circuit includes a delay module that receives the start burst signal and that generates a delayed start burst signal. An enable signal generator receives the delayed start burst signal and generates an enable signal. A first circuit generates the qualified data read strobe signal based on the enable signal and the bidirectional data strobe signal.

Qualified data strobe signal for double data rate memory controller module

Growing community of inventors

Moshav Lachish, Israel

Haggai Telem