Samsung Electronics Co., Ltd.

Haewon Lee

Jieun Shin

Seungwook Lee

Hocheol Bang

Sang Kyu Kang

Mihye Kim

Jiwon Park

Jiwon Lee

Younghwan Park

Moosup Lim

Sang-Kyu Kang

Kang-sun Lee

Donghyuk Park

Kwanyoung Oh

Dongjoo Yang

Ho-Cheol Bang

Sangjoo Lee

A semiconductor memory device includes a memory cell array including a plurality of memory cells and a control logic circuit configured to control the semiconductor memory device. The control logic circuit includes a mode register and a remaining lifetime calculating device configured to count usage metrics based on one or more of the following: a number of clock signals received from a memory controller, an amount of data transmitted or received to or from the memory controller, and/or a number of commands received from the memory controller. The remaining lifetime calculating device generates a remaining lifetime code representing a remaining lifetime of the semiconductor memory device based on the usage metrics, and stores the remaining lifetime code in the mode register.

Semiconductor memory device and memory system

In some embodiments, a memory system includes a memory device and a host configured to transmit, to the memory device, a command and address (C/A) signal and a clock signal, and to transmit or receive data signals to or from the memory device. Each command that is configured to access the memory device is associated with an access timing parameter. The memory device includes an access parameter timer configured to measure an actual timing value of the access timing parameter, a spec register configured to provide a spec timing value defining an effective timing of the access timing parameter, a comparison circuit configured to compare the actual timing value and the spec timing value, and a mode register configured to store an access timing violation flag that is read by the host when the actual timing value deviates from the spec timing value by exceeding a predetermined range.

Memory device, memory system and method for operating memory system

An image sensor includes a first floating diffusion region, a second floating diffusion region adjacent to the first floating diffusion region in a first direction, a third floating diffusion region adjacent to the first floating diffusion region in a second direction that is perpendicular to the first direction and a fourth floating diffusion region adjacent to the second floating diffusion region in the second direction. A pad is disposed on the first and second floating diffusion regions. The pad at least partially overlaps the first and second floating diffusion regions. The image sensor includes an interconnection line and a first contact connecting the pad to the interconnection line. A first surface of the pad is disposed on the first floating diffusion region and the second floating diffusion region. A device isolation pattern defines the first, second, third and fourth floating diffusion regions.

Image sensor

An image sensor includes a substrate that includes first and second surfaces that oppose each other in a first direction and pixel areas arranged in directions parallel to the first surface, a first device isolation film that separates the pixel areas, four photodiodes disposed in each of the pixel areas inside of the substrate, and arranged in a 2×2 array, a second device isolation film that separates the four photodiodes from each other, a color filter disposed on the first surface of the substrate, and that includes four regions that respectively correspond to the four photodiodes, wherein each region has a convex upper surface, and a first microlens disposed above the color filter and that corresponds to each of the pixel areas. Accordingly, in the image sensor, light incident on the internal device isolation film is reduced, and loss of autofocusing sensitivity of the image sensor is reduced.

Image sensor with color filters with convex surfaces

A semiconductor memory device includes a mammy cell array including a plurality of memory cells and a control logic circuit configured to control the semiconductor memory device. The control logic circuit includes a mode register and a remaining lifetime calculating device configured to count usage metrics based on one or more of the following: a number of clock signals received from a memory controller, an amount of data transmitted or received to or from the memory controller, and/or a number of commands received from the memory controller. The remaining lifetime calculating device generates a remaining lifetime code representing a remaining lifetime of the semiconductor memory device based on the usage metrics, and stores the remaining lifetime code in the mode register.

An image sensor includes a separation impurity layer in a semiconductor layer and defining a photoelectric conversion region and a readout circuit region, a photoelectric conversion layer in the semiconductor layer of the photoelectric conversion region and surrounded by the separation impurity layer, a floating diffusion region spaced apart from the photoelectric conversion layer and in the semiconductor layer of the photoelectric conversion region, a transfer gate electrode between the photoelectric conversion layer and the floating diffusion region, and impurity regions in the semiconductor layer of the readout circuit region. When the photoelectric conversion layer is integrated with photo-charges, the separation impurity layer has a first potential level around the photoelectric conversion layer and a second potential level on a portion between the photoelectric conversion layer and the impurity regions of the readout circuit region. The second potential level is greater than the first potential level.

Growing community of inventors

Yongin-si, South Korea

Haewon Lee