Samsung Electronics Co., Ltd.

Hae Young Chung

Hangi Jung

Wangsoo Kim

Heon Su Jeong

Su Jin Son

Hyung Ryong Moon

Soyeong Shin

YongHyun An

Hye Jin An

A memory device includes a memory cell array and an input/output circuit. The input/output circuit is configured to: (i) generate second data in response to sampling first data by comparing the first data against a reference voltage, (ii) generate an offset calibration code corresponding to a first input offset of the input/output circuit based on the second data, prior to receiving a mode register code, (iii) change a gain of an input buffer corresponding to the mode register code after receiving the mode register code, and (iv) calibrate a second input offset corresponding to the changed gain of the input buffer by adjusting a current amount applied to a current element electrically connected to an input terminal of the input buffer based on the offset calibration code and the mode register code. Control logic may also be used to provide the mode register code, which includes gain information associated with the input/output circuit, to the input/output circuit.

Memory systems and devices that support methods for calibrating input offsets therein

A memory device of a memory module includes a CA buffer that receives a command/address (CA) signal through a bus shared by a memory device different from the memory device of the memory module, and a calibration logic circuit that identifies location information of the memory device on the bus. The memory device recognizes its own location on a bus in a memory module to perform self-calibration, and thus, the memory device appropriately operates even under an operation condition varying depending on a location in the memory module.

Memory device performing self-calibration by identifying location information and memory module including the same

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Seongnam-si, South Korea

Hae Young Chung