Skhynix Inc.

Hynix Semiconductor Inc.

Seoul National University

Hae Rang Choi

Yong Ju Kim

Jae Min Jang

Hyung Soo Kim

Ji Wang Lee

Tae Jin Hwang

Ic Su Oh

Hee Woong Song

Sung Woo Han

Chang Kun Park

Dae Han Kwon

Seong Hwi Song

Won Joo Yun

Hyung Sik Won

Sungjoo Yoo

Kun Woo Park

Dan Han Kwon

A semiconductor device includes a cell circuit including a plurality of memory arrays, and a control circuit configured to control the cell circuit. A memory array of the plurality of memory arrays has a plurality of sub-arrays including a first sub-array and a second sub array, and an array connecting circuit configured to connect bit lines of the first sub-array to respective corresponding bit lines of the second sub-array according to a copy signal. The semiconductor device may further include a partial sum circuit configured to perform charge sharing between a plurality of bit lines of the first sub-array.

Semiconductor device performing in-memory processing and operation method thereof

A semiconductor device may be provided. The semiconductor device may include a memory area. The memory area may be configured to compare an address with a first failure address and a second failure address to store an input datum into a redundancy area and to output the stored input datum as an output datum or configured to compare the address with the first and failure addresses to correct an error of an input datum stored in a normal area to output the corrected input datum as the output datum. The semiconductor device may include a failure address storage circuit. The failure address storage circuit may be configured to store the address as a first failure address based on a first retention information signal and configured to store the address as a second failure address based on a second retention information signal.

Semiconductor devices and semiconductor systems including the same

An integrated circuit may be provided. The integrated circuit may include a transmitter and a receiver. The transmitter outputs first transmission data to a first channel and outputs second transmission data to a second channel. The phase of the first transmission data transmitted through the first channel is different from a phase of the second transmission data transmitted through the second channel.

Integrated circuits relating to transmission data and latch clock signals

Semiconductor devices are provided. The semiconductor device may include a current generation circuit and an internal circuit. The current generation circuit may include a first drive element and a second drive element which are connected in series. The current generation circuit may generate a reference voltage signal whose voltage level is set by a reference current which is identical or substantially identical to a current flowing through the first and second drive elements. The internal circuit may utilize an output current controlled according to the reference current as an operation current thereof.

Current generation circuits and semiconductor devices including the same

A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power.

Semiconductor memory device having pads

An internal control signal regulation circuit includes a programming test unit configured to detect an internal control signal in response to an external control signal and generate a selection signal, test codes and a programming enable signal; and a code processing unit configured to receive the test codes or programming codes in response to the selection signal and regulate the internal control signal.

Internal control signal regulation circuit

A delay circuit includes a clock delay line, a command delay line, a delay line control block, and a shared shift register block. The clock delay line delays an input clock and generates a delayed clock. The command delay line delays a command signal and generates a delayed command signal. The delay line control block generates a control signal according to a result of comparing phases of a feedback clock which is generated as the delayed clock is delayed by a modeled delay value and the input clock. The shared shift register block sets delay amounts of the clock delay line and the command delay line to be substantially the same with each other, in response to the control signal.

Delay circuit and semiconductor apparatus including the same

A clock generation circuit includes a delay line, a delay modeling block, a phase detection block, a multi-update signal generation block, and a delay line. The delay line delays an input clock and generates a delayed clock. The delay modeling block delays the delayed clock by a modeled delay value and generates a feedback clock. The phase detection block compares phases of the input clock and the feedback clock and generates phase information, and quantizes a phase difference between the input clock and the feedback clock and generates phase codes. The multi-update signal generation block generates a multi-update signal in response to the phase codes. The delay line control block changes a delay amount of the delay line in response to the multi-update signal and the phase information.

Clock generation circuit and semiconductor apparatus including the same

An on-die termination circuit includes a reference period signal generation circuit that generates a reference period signal according to a level of a reference voltage, a first period signal generation circuit that generates a first period signal according to a voltage level of a pad, a period comparison circuit that compares a period of the first period signal with a period of the reference period signal and count a plurality of driving signals, and a driver circuit that drives the pad in response to the plurality of driving signals.

On-die termination circuit

A reset signal generation apparatus includes a reset signal generation unit and a reset signal expansion unit. The reset signal generation unit enables a reset signal and an enable signal in response to a reset input signal, and disables the reset signal in response to a pulse width extension signal. The reset signal expansion unit generates the pulse width extension signal that is enabled for a predetermined time, in response to the enable signal.

Device for generating reset signal having sufficient pulse width

A clock generation circuit includes a delay line, which delays an input clock and generates a delayed clock, a delay modeling unit, which delays the delayed clock by a modeled delay value and generates a feedback clock, a phase detection unit, which compares phases of the input clock and the feedback clock and generates a phase detection signal, a filter unit, which receives the phase detection signal and generates phase information, generates an update signal when a difference between the numbers of phase detection signals with a first and a second level generated is greater than or equal to a threshold value, and generates the update signal after a lapse of a predetermined time when the difference is less than the threshold value, and a delay line control unit, which sets a delay value of the delay line in response to the update signal and the phase information.

Delay control circuit and clock generation circuit including the same

A clock signal duty correction circuit includes: a first transition timing control unit configured to generate a first control signal for controlling a rising timing of a duty correction clock signal by using a clock signal; a second transition timing control unit configured to generate a second control signal for varying a falling timing of the duty correction clock signal by using the clock signal according to a code signal; and a differential buffer unit configured to generate the duty correction clock signal, whose rising time or falling time is adjusted, in response to the first control signal and the second control signal.

Growing community of inventors

Icheon-si, South Korea

Hae Rang Choi