Skhynix Inc.

Postech Academy-industry Foundation

Northeastern University

Hae Kang Jung

Hong June Park

Yong Ju Kim

Yong Suk Choi

Sun Ki Cho

Hong Joo Song

Kyoung Ho Lee

Ji Hoon Lim

Yong Bin Kim

Chang Kyu Choi

Dae-Han Kwon

Keun Soo Song

Tae Jin Hwang

Jun Yong Song

Dong Uc Ko

Yang Ho Sur

Soo Min Lee

Joo Hwan Cho

Hongjoo Song

Sung Gil Jang

Soo Mln Lee

Min Sung Cheon

Gyunam Jeon

A system includes a data transmission unit, a termination resistor and a data reception unit. The data transmission unit may drive a data transmission line based on data, and drive the data transmission line to a voltage level corresponding to a termination voltage during a specified operation period. The termination resistor may be coupled between the data transmission line and a termination node. The data reception unit may receive a signal transmitted through the data transmission line.

System and interface circuit for driving data transmission line to termination voltage

A buffer circuit configured to receive first and second input signals through first and second input transistors coupled to a first power voltage node, output a first output signal through a first output node and a second output signal through a second output node based on the first and second input signals. A load circuit is coupled among the first output node, the second output node, and a second power voltage node and a resistance value is adjusted based on at least one of the first and second output signals.

Buffer circuit

A circuit may include a transmitter for generating a signal indicative of input data, an on-chip channel for transmitting the signal from the transmitter, and a receiver comprising a receiving terminal that has a negative resistance value as input resistance of the receiving terminal, the receiver generating a signal indicative of recovered data based on the transmitted signal through the on-chip channel. The circuit may recycle a portion of charge stored in the on-chip channel using charge recycling, and the charge recycling is associated with the negative resistance value of the input resistance.

Transmitter and receiver circuits

A data transmission circuit includes a data bus inversion encoding circuit configured to compare previous output data and current output data, invert or non-invert the current output data to control the number of data transitions; and transmitters configured to drive signal transmission lines based on outputs of the data bus inversion encoding circuit.

Data transmission circuit for operating a data bus inversion, and a semiconductor apparatus and a semiconductor system including the same

A semiconductor apparatus may include a receiver circuit and a termination circuit. The receiver circuit may be coupled to a receiving node, and configured to receive a signal transmitted through a signal transmission line. The termination circuit may be configured to be turned on to set a resistance value of the receiving node in a transition period of the signal, and turned off in a stabilization period of the signal.

Dynamic termination circuit, semiconductor apparatus and system including the same

A receiver circuit receives a signal from a semiconductor device. The receiver circuit includes an input buffer including a first plurality of transistors, the input buffer being configured to detect a fabrication condition of the receiver circuit, generate a control signal according to the detected fabrication condition, and control a gain of an input signal by adjusting a number of operating transistors among the first plurality of transistors in response to the control signal; and a latch circuit configured to latch an output signal of the input buffer, and adjust threshold voltages of a second plurality of transistors in response to a test signal.

Receiver circuit

A semiconductor apparatus includes a first chip and a second chip. The first chip provides a first termination control signal to the second chip and the second chip provides a termination resistance for the first chip based on the first termination control signal, when the first chip receives data.

Semiconductor apparatus related to termination and semiconductor system including the semiconductor apparatus

A transmitting circuit may include a clock generation circuit and a serializer. The clock generation circuit may generate a plurality of output clock signals by performing an emphasis operation for a plurality of clock signals based on a plurality of data. The serializer may output the plurality of data as output data in synchronization with the plurality of output clock signals.

Transmitting circuit, semiconductor apparatus and semiconductor system configured to use the transmitting circuit

A semiconductor package for performing a reset operation includes a first semiconductor device including a first resistor element coupled to a reset pin, the first semiconductor device configured to be applied with a reset signal through the reset pin such that the reset operation is performed. The semiconductor package includes a second semiconductor device including a second resistor element coupled to the reset pin, the second semiconductor device configured to be applied with the reset signal through the reset pin such that the reset operation is performed. The first resistor element and the second resistor element may be selectively coupled to the reset pin when the reset operation is performed.

Semiconductor package and semiconductor system related to performing a reset operation

A transmitting device includes a calibration circuit and a transmission circuit. The calibration circuit generates calibration codes by performing a calibration operation. The calibration circuit also generates compensation calibration codes by increasing or decreasing values of the calibration codes according to whether a number of codes among the calibration codes having a predetermined level is greater than or equal to a threshold value. The transmission circuit drives a signal transmission line based on an input signal and the compensation calibration codes.

Transmitting device using calibration circuit, semiconductor apparatus and system including the same

Data transmission circuit with encoding circuit, and semiconductor apparatus and semiconductor system including the data transmission circuit

A semiconductor device may include a calibration circuit and an output circuit. The calibration circuit may perform a calibration operation for setting a resistance value of the output circuit. The calibrations circuit may perform the calibration operation by being coupled, through a signal transmission line, to a reference resistor provided in another semiconductor device.

Growing community of inventors

Gwangmyeong-si, South Korea

Hae Kang Jung