Rambus Inc.

Altera Corporation

Texas Instruments Corporation

Lattice Semiconductor Corporation

Silicon Image Gmbh

Hae-Chang Lee

Brian S Leibowitz

Jihong Ren

Jared L Zerbe

Jaeha Kim

Qi Lin

Jade M Kizer

Carl William Werner

Fariborz Assaderaghi

Yohan Usthavia Frans

Nhat M Nguyen

Simon Li

Kyung Suk Oh

Akash Bansal

Thomas Hastings Greer

Ruwan Ratnayake

Jafar Savoj

Thomas H Greer, Iii

Mark A Horowitz

Kun-Yung Chang

Farshid Aryanfar

Arnold Robert Feldman

Ting Wu

Andrew Keith Joy

Masoud Koochakzadeh

Sergey Yuryevich Shumarayev

Tim Tri Hoang

Boon Jin Ang

Jie Shen

Yanjing Ke

Kashinath Ullhas Prabhu

Yujeong Shim

Guang Chen

Wenyi Jin

Brian Liebowitz

Heetae Ahn

Ken Kun-Yung Chang

Thomas H Iii Greer

Kashinath Prabhu

Thomas H Greer Iii

A device includes a transmitter coupled to a node, where the node is to couple to a wired link. The transmitter has a plurality of modes of operation including a calibration mode in which a range of communication data rates over the wired link is determined in accordance with a voltage margin corresponding to the wired link at a predetermined error rate. The range of communication data rates includes a maximum data rate, which can be a non-integer multiple of an initial data rate.

Interface with variable data rate

An integrated circuit (IC) chip includes transfer circuitry to transfer signals between the IC chip and a second IC chip. The transfer circuitry includes equalization circuitry having at least one tap to equalize the signals. The equalization circuitry includes a tap weight adapter circuit to generate a respective tap weight for each of the at least one tap based on edge information of previously transferred signals.

Edge based partial response equalization

A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.

High-speed signaling systems and methods with adaptable, continuous-time equalization

A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

Methods and circuits for asymmetric distribution of channel equalization between devices

An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.

Integrated circuit having receiver jitter tolerance ('JTOL') measurement

An intergrated circuit (IC) chip includes receiver circuitry to receive signals from a second IC chip. The receiver circuitry includes equalization circuitry having at least one tap to equalize the signals. The equalization circuitry includes a tap weight adapter circuit to generate at least one tap weight corresponding to the at least one tap based on edge information of previously received signals.

A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.

Receiver with enhanced clock and data recovery

A circuit for performing clock recovery according to a received digital signal. The circuit includes at least an edge sampler and a data sampler for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock and data clock signals offset in phase from one another to the respective clock inputs of the edge sampler and the data sampler. A digital phase detector determines if the data clock is early, late or synchronized with respect to data value transitions in the digital signal, and based on that determination provides a phase adjustment signal to the clock signal supply circuit, which is operable to vary phases of the data and edge clock signals accordingly.

Phase control block for managing multiple clock domains in systems with frequency offsets

A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.

Receiver with clock recovery circuit and adaptive sample and equalizer timing

Integrated circuit that injects offsets into recovered clock to simulate presence of jitter in input signal

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Los Altos, CA, United States of America

Hae-Chang Lee