Nec Corporation

Hachiro Sawada

Hideaki Honma

Ken-ichi Takahashi

Tadashi Fujitsu

In a display managing arrangement comprising a display memory and a display memory controller for accessing the display memory to display a selected area of an image datum with the selected area scrolled on the image datum or otherwise subjected to management, the display memory is divided into memory blocks arranged as an N-row M-column matrix. Each memory block is for use as a unit of the management and is divisible into memory elements arranged as an n-row m-column matrix. When the memory elements of the display memory are assigned with serial memory element addresses along each row of the memory elements of the display memory and then along a next column-wise downward row, the memory controller may access the memory elements of selected ones of the memory blocks in block parallel by specifying the serial memory element addresses for each memory block on the one hand from a least memory element address in the memory block under consideration consecutively to the serial memory element address which is equal to the least memory element address plus the number m less one. On the other hand, the serial memory element addresses are specified discretely along one of the m columns by adding products of a step value mM and multipliers variable from zero to the number n less one to one of the serial memory element addresses that is congruent with the least memory element address modulo the step value. On storing the selected area in the display memory, the image datum may likewise be accessed.

Display managing arrangement with a display memory divided into a matrix

In an image rotating device, an input data processor processes an input signal representative of an original image into a processed signal successively representative of words wherein bits representative of picture elements of the original image are arranged according to an angle of rotation of 90.degree., 180.degree., or 270.degree. which should be given to the original image. When the rotation is 90.degree. or 270.degree., a block of bits is set in a shift register array which successively produces groups of bits. The groups of bits are stored in a random access memory and then read therefrom as successive group sets in a predetermined manner. An output data processor processes the group sets into an output signal representative of a desired rotated output image. When the rotation is 180.degree., the processed signal is processed by the output data processor directly into the output signal. Preferably, a prescribed number of shift register arrays are used to successively produce the groups, each having a longer bit length than the group produced by a single shift register array.

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Tokyo, Japan

Hachiro Sawada