International Business Machines Corporation

Globalfoundries Singapore Pte. Ltd.

Advanced Micro Devices Corporation

Infineon Technologies North America Corp.

Toshiba America Electronic Components, Inc.

Süss Microtec Photomask Equipment Gmbh & Co. Kg

Habib Hichri

Matthew S Angyal

Vincent James McGahay

Richard Stephan Wise

Kelly Malone

Theodorus E Standaert

Conal Eugene Murray

Xiang Hu

Jia Lee

Stephen McConnell Gates

Kevin Shawn Petrarca

John Anthony Fitzsimmons

Thomas M Shaw

Xiao Hu Liu

Terry Allen Spooner

Sean David Burns

Stephen Edward Greco

Xi Li

Colin J Brodsky

Catherine B Labelle

Richard Stephen Wise

Jawahar P Nayak

Glenn A Biery

Jeffrey R Marino

Bernd E Kastenmeier

Arthur W Martin

Sanjit Kumar Das

Mary Jane Brodsky

Lawrence Alfred Clevenger

Daniel C Edelstein

Timothy Joseph Dalton

Christopher J Penny

Richard Paul Volant

Chandrasekhar Narayan

Kaushik Arun Kumar

Michael Wayne Lane

Ian D Melville

William Francis Landers

Ahmad D Katnani

Ravi Prakash Srivastava

Charles Robert Davis

Brett H Engel

Craig Child

Dale Curtis McHerron

Uwe Dietze

Ronald Anthony DellaGuardia

Helen Wang

Peter E Biolsi

Andrew Lu

Hakeem B S Akinmade-Yusuff

Edward Paul Barth

Brian Wayne Herbst

Narender N Rana

Giovanni Fiorenza

Oluwafemi O Ogunsola

David K Watts

Davide Dattilo

Martin Samayoa

Arifuzzaman (Arif) Sheikh

Seongkuk Lee

Kimberly A Larsen

Helen L Maynard

Muhammed Shafi Kurikka Valappil Pallachalil

Hideshi Miyajima

Kimberly Larsen

Helen c/o Ibm UK Limited IPL Maynard

A method and an apparatus for cleaning a substrate having at least one surface having a residue to be removed thereon is described. The method comprises: scanning at least an area of the surface having the residue thereon with laser light to thereby heat the surface and the residue; controlling the heating so that a part of the residue first liquefies such that the liquefied part of the residue starts flowing towards the solid part of the residue, thereby forming a meniscus with the solid part of the residue and accumulating in part on top of the solid part, the thus generated thicker layer of residue absorbing further heat to be decomposed or vaporized.

Method and apparatus for cleaning a substrate and computer program product

Antireflective residues during pattern transfer and consequential short circuiting are eliminated by employing an underlying sacrificial layer to ensure complete removal of the antireflective layer. Embodiments include forming a hard mask layer over a conductive layer, e.g., a silicon substrate, forming the sacrificial layer over the hard mask layer, forming an optical dispersive layer over the sacrificial layer, forming a silicon anti-reflective coating layer over the optical dispersive layer, forming a photoresist layer over the silicon anti-reflective coating layer, where the photoresist layer defines a pattern, etching to transfer the pattern to the hard mask layer, and stripping at least the optical dispersive layer and the sacrificial layer.

ARC residue-free etching

Embodiments of the invention may include first providing a stack of layers including a semiconductor substrate, a buried oxide layer on the semiconductor substrate, a semiconductor-on-insulator layer on the buried-oxide layer, a nitride layer on the semiconductor-on-insulator layer, and a silicon oxide layer on the nitride layer. A first opening and second opening with a smaller cross-sectional area than the first opening are then formed in the silicon oxide layer, the nitride layer, the semiconductor-on-insulator layer, and the buried-oxide layer. The first opening and the second opening are then etched with a first etching gas. The first opening and the second opening are then etched with a second etching gas, which includes the first etching gas and a halogenated silicon compound, for example, silicon tetrafluoride or silicon tetrachloride. In one embodiment, the first etching gas includes hydrogen bromide, nitrogen trifluoride, and oxygen.

Method for simultaneously forming features of different depths in a semiconductor substrate

A method of forming a device is disclosed. The method includes providing a substrate prepared with a dielectric layer having first and second regions. The first region comprises wide features and the second region comprises narrow features. A depth delta exists between bottoms of the wide and narrow features. A non-conformal layer is formed on the substrate and it lines the wide and narrow trenches in the first and second regions. The non-conformal layer is removed. Removing the non-conformal layer reduces the depth delta between the bottoms of the wide and narrow features in the first and second region.

Method to reduce depth delta between dense and wide features in dual damascene structures

A metal seed composition useful in seeding a metal diffusion barrier or conductive metal layer on a semiconductor or dielectric substrate, the composition comprising: a nanoscopic metal component that includes a metal useful as a metal diffusion barrier or conductive metal; an adhesive component for attaching said nanoscopic metal component on said semiconductor or dielectric substrate; and a linker component that links said nanoscopic metal component with said adhesive component. Semiconductor and dielectric substrates coated with the seed compositions, as well as methods for depositing the seed compositions, are also described.

Conductive metal and diffusion barrier seed compositions, and methods of use in semiconductor and interlevel dielectric substrates

A method of manufacturing an integrated circuit system includes: providing a substrate; forming a polysilicon layer over the substrate; forming an anti-reflective coating layer over the polysilicon layer; etching an anti-reflective coating pattern into the anti-reflective coating layer leaving an anti-reflective coating residue over the polysilicon layer; and etching the anti-reflective coating residue with an etchant gas mixture comprising hydrogen bromide, chlorine, and oxygen to remove the anti-reflective coating residue for mitigating the formation of a polysilicon protrusion.

Integrated circuit system with reduced polysilicon residue and method of manufacture thereof

Inspection methods. A method includes adhering an optical blocking layer directly onto and in direct mechanical contact with a semiconductor process wafer, the blocking layer being substantially opaque to a range of wavelengths of light; applying at least one layer over the blocking layer; and inspecting optically at least one wavelength at least one inspection area, the blocking layer extending substantially throughout the inspection area. An inspection method including adhering an optical absorbing layer to a semiconductor process wafer, where the absorbing layer is configured to substantially absorb a range of wavelengths of light; applying at least one layer over the absorbing layer; and inspecting optically at least one wavelength at least one inspection area of the process wafer. A manufacturing method including ascertaining if a defect is present within a photoresist layer, and changing a semiconductor manufacturing process to prevent the defect, if the defect is present.

Optical inspection methods

A method of forming a trench in a semiconductor device formed of a substrate and a first layer formed over the substrate includes forming an initial trench that passes through the first layer to the substrate, the initial trench having a diameter that decreases from a first diameter to a second diameter, the second diameter being measured at a distance closer to the substrate than the first diameter; exposing the trench to a dopant via an orthogonal ion implant to form doped regions sidewalls of the trench; and etching the trench to remove at least some of the doped regions.

Liner protection in deep trench etching

A method for integrating cap liner formation in back-end-of-line (BEOL) processing of a semiconductor device includes forming a trench structure within an insulating layer of the semiconductor device, depositing a first liner material over a top surface of the insulating layer, including sidewall and bottom surfaces of the trench, and partially filling the trench with a wiring metal material to a height corresponding to a final intended line height. A second liner material is over the wiring metal material, and a sacrificial fill material is formed over the second liner material. The sacrificial fill is planarized down to the level of the second liner material over the wiring metal material partially filling the trench, wherein a remaining portion of the second liner material defines a cap liner of the wiring metal.

Method for integrating liner formation in back end of line processing

A system, a method and a computer program product for analyzing a circuit design provide for discretizing the circuit design into a series of pixels. A fraction of at least one constituent material is determined for each pixel. A deflection is also determined for each pixel. The deflection is predicated upon a planarizing of the pixel, and it is calculated while utilizing an algorithm that includes the fraction of the at least one constituent material. A series of deflections for the series of pixels may be mapped and evaluated.

Deflection analysis system and method for circuit design

Stacked via pillars, such as metal via pillars, are provided at different and designated locations in IC chips to support the chip structure during processing and any related processing stresses such as thermal and mechanical stresses. These stacked via pillars connect and extend from a base substrate of the strip to a top oxide cap of the chip. The primary purpose of the stacked via pillars is to hold the chip structure together to accommodate any radial deformations and also to relieve any stress, thermal and/or mechanical, build-tip during processing or reliability testing. The stacked via pillars are generally not electrically connected to any active lines or vias, however in some embodiments the stacked via pillars can provide an additional function of providing an electrical connection in the chip.

Building metal pillars in a chip for structure support

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Poughkeepsie, NY, United States of America

Habib Hichri