Oracle America, Inc.

Oracle International Corporation

Haakan E Zeffer

Robert Cypher

Shailender Chaudhry

Anders Landin

Brian McGee

Bharat K Daga

Some embodiments of the present invention provide a system for operating a store queue, wherein the store queue buffers stores that are waiting to be committed to a memory system in a processor. During operation, the system examines an entry at the head of the store queue. If the entry contains a membar token, the system examines an unacknowledged counter that keeps track of the number of store operations that have been sent from the store queue to the memory system but have not been acknowledged as being committed to the memory system. If the unacknowledged counter is non-zero, the system waits until the unacknowledged counter equals zero, and then removes the membar token from the store queue.

Store queue with token to facilitate efficient thread synchronization

Some embodiments of the present invention provide a system that performs stores in a memory system. During operation, the system performs a store for a first thread, which involves creating an entry for the store in a store queue for the first thread. It also involves attempting to store-mark a corresponding cache line for the first thread by sending a store-mark request for the first thread to the memory system, wherein a store-mark on the cache line indicates that one or more store queue entries are waiting to be committed to the cache line. If the attempt to store-mark the cache line fails because a second thread holds a store-mark on the cache line, and if obtaining the store-mark will ensure forward progress for the first thread, the system forces the second thread to release the store-mark, so the first thread can acquire a store-mark for the cache line.

Store queue with store-merging and forward-progress guarantees

Some described embodiments provide a system that performs stores in a memory system. During operation, the system receives a store for a first thread. The system then creates an entry for the store in a store queue for the first thread. While creating the entry, the system requests a store-mark for a cache line for the store, wherein the store-mark for the cache line indicates that one or more store queue entries are waiting to be committed to the cache line. The system then receives a response to the request for the store-mark, wherein the response indicates that the cache line for the store is store-marked. Upon receiving the response, the system updates a set of ordered records for the first thread by inserting data for the store in the set of ordered records, wherein the set of ordered records include store-marked stores for the first thread.

Store queue supporting ordered and unordered stores

Some embodiments of the present invention provide a system that avoids deadlock while attempting to acquire store-marks on cache lines. During operation, the system keeps track of store-mark requests that arise during execution of a thread, wherein a store-mark on a cache line indicates that one or more associated store buffer entries are waiting to be committed to the cache line. In this system, store-mark requests are processed in a pipelined manner, which allows a store-mark request to be initiated before preceding store-mark requests for the same thread complete. Next, if a store-mark request fails, within a bounded amount of time, the system removes or prevents store-marks associated with younger store-mark requests for the same thread, thereby avoiding a potential deadlock that can arise when one or more other threads attempt to store-mark the same cache lines.

Deadlock avoidance during store-mark acquisition

Embodiments of the present invention provide a system that performs a speculative writestream transaction. The system starts by receiving, at a home node, a writestream ordered (WSO) request to start a WSO transaction from a processing subsystem. The WSO request identifies a cache line to be written during the WSO transaction. The system then sends an acknowledge signal to the processing subsystem to enable the processing subsystem to proceed with the WSO transaction. During the WSO transaction, the system receives a second WSO request to start a WSO transaction. The second WSO request identifies the same cache line as to be written during the subsequent WSO transaction. In response to receiving the second WSO request, the system sends an abort signal to cause the processing subsystem to abort the WSO transaction.

Speculative writestream transaction

The present invention is directed to a system managing data in a multilevel cache memory system. Certain cache data is designated and stored only in particular levels of the multilevel cache, bypassing other levels of the multilevel cache. In a multiprocessor environment, the present invention includes cache coherency operations or messages that pertain to data stored only in certain levels of a multilevel cache.

Cache hierarchy with bounds on levels accessed

Some embodiments of the present invention provide a system that processes a request for a cache line in a multiprocessor system that supports a directory-based cache-coherence scheme. During operation, the system receives the request for the cache line from a requesting node at a home node, wherein the home node maintains directory information for all or a subset of the address space which includes the cache line. Next, the system performs an action at the home node, which causes a valid copy of the cache line to be sent to the requesting node. The system then completes processing of the request at the home node without waiting for an acknowledgment indicating that the requesting node received the valid copy of the cache line.

Bandwidth-efficient directory-based coherence protocol

Some embodiments of the present invention provide a system that acquires a lock in a shared memory multiprocessor system. During operation, the system loads the lock into a cache associated with the thread and then reads a value of the lock. If the value indicates that the lock is currently held by another thread, the system periodically executes an instruction that tests a status of the lock. If the status indicates the lock is valid, the system continues to test the status of the lock. Otherwise, if the status indicates that the lock was invalidated by a store, the system attempts to acquire the lock by executing an atomic operation. On the other hand, if the status indicates that the lock was invalidated by an atomic operation, or that the lock is not present in the cache, the system repeats the loading and reading operations.

Supporting efficient spin-locks and other types of synchronization in a cache-coherent multiprocessor system

Embodiments of the present invention provide a system that selectively performs lookups for cache lines. During operation, the system by maintains a lower-level cache and a higher-level cache in accordance with a set of rules that dictate conditions under which cache lines are held in the lower-level cache and the higher-level cache. The system next performs a lookup for cache line A in the lower level cache. The system then discovers that the lookup for cache line A missed in the lower-level cache, but that cache line B is present in the lower-level cache. Next, in accordance with the set of rules, the system determines, without performing a lookup for cache line A in the higher-level cache, that cache line A is guaranteed not to be present and valid in the higher-level cache because cache line B is present in the lower-level cache.

Selectively performing lookups for cache lines

Embodiments of the present invention provide a system that maintains coherence between cache lines in a computer system by using dynamic privatization. During operation, the system starts by receiving a request for a read-only copy of a cache line from a processor. The system then determines if the processor has privately requested the cache line a predetermined number of times. If so, the system provides a copy of the cache line to the processor in an exclusive state. Otherwise, the system provides a copy of the cache line to the processor in a shared state.

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Santa Clara, CA, United States of America

Haakan E Zeffer