Oracle International Corporation

Sun Microsystems, Inc.

New Jersey Institute of Technology

Ha Pham

Jin-Uk Shin

Changku Hwang

Sebastian Turullols

Robert Paul Masleid

Ishwardutt Parulkar

Qing Xie

Yifan YangGong

He Huang

Jin-uk Shin

Daisy Jian

Hoki Kim

Mayur Joshi

Darius Sollohub

Hiep Ngo

Vaibhav Gupta

A method and apparatus for calibrating a temperature sensor is disclosed. In one embodiment, a method comprises generating first and second digital values based respectively on first and second voltages applied to a portion of a temperature sensor circuit. An arithmetic circuit may derive the value of the second voltage based on the first and second digital values. The method further comprises determining an initial value of a constant based on values of the first and second voltages, and determining a final value of the constant based on the initial voltage and at least one voltage offset. The constant may then be used in determining temperature readings for the temperature sensor.

Statistical temperature sensor calibration apparatus and methodology

Window or curtain wall assemblies and concealed window fastening assemblies are disclosed. Each window panel includes two layers of glass or other material separated by a spacing mullion, which lines the perimeter of the window panel to create a sealed chamber. The depth of the sealed chamber between the two layers is variable to accommodate either thermal requirements, vertical and horizontal structural loads, or both. The chamber reduces heat loss due to convection allowing it to outperform current double or triple glazing window walls. Each chamber can connect through tubes to allow for air or gas transfer to enhance thermal performance and create the potential for other functional and aesthetic effects. When the window panels are assembled, the latching mechanism structurally unifies each panel to become a single monolithic surface that can also account for thermal expansion. Elements of the latching mechanism are arranged to allow the window or curtain wall to be assembled from the interior, leaving only caulking to be performed from the exterior. Concealing all of such elements helps eliminate the exposure of window mullions and minimizes maintenance of the window or curtain wall.

Concealed fastener window or curtain wall assemblies

Embodiments of a temperature sensing apparatus are disclosed. The apparatus may include a voltage generator and circuitry. The voltage generator may generate a first voltage level and a second voltage level dependent on an operating temperature. In response to a given change in the operating temperature, the first and second voltage levels may change, with the second voltage level changing by a different amount than the first voltage level. The voltage generator may generate a third voltage level. The circuitry may measure the first voltage level, the second voltage level, and the third voltage level, and may calculate the operating temperature dependent on a ratio of a difference between the first voltage level and the second voltage level and the third voltage level.

High accuracy, compact on-chip temperature sensor

A double half latch circuit includes a first stage coupled to receive a local input enable signal on an input of a second logic gate, and a complement of the clock signal on an input of a third logic gate, and further includes a fourth logic gate coupled to generate an intermediate enable signal based on states of the local input enable signal the complement of the clock signal. A second stage includes a fifth logic gate coupled to receive the complement of the clock signal, and a sixth logic gate coupled to receive the intermediate enable signal, and is configured to generate the output enable signal. The double half-latch circuit is transparent to the state changes of the local input enable signal when the clock signal is low and opaque to state changes of the local input enable signal when the clock signal is high.

Double half latch for clock gating

A flip-flop circuit is disclosed. The flip-flop circuit includes pull-up and pull-down circuits each coupled to a data input and configured to be activated responsive to a clock signal transition from a first phase to a second phase, depending on the input data. A write circuit is configured to write data into a latch of the flip-flop responsive to activation of one of the pull-up and pull-down circuits. An output driver circuit includes a dynamic portion and a static portion, with the dynamic portion being activated responsive to activation of one of the pull-up and pull-down circuits. Activation of the dynamic portion may occur concurrently with writing of the data into the latch. The output driver circuit also includes a static portion. After the clock transitions back to the first phase, the static portion may drive and hold the output while the dynamic portion is deactivated.

High speed dynamic flip-flop circuit with split output driver

Embodiments of a flip-flip circuit are disclosed that may allow a reduction in data setup time and lower switching power. The flip-flop circuit may include an input circuit, an output circuit, a clock circuit, and a feedback circuit. The clock circuit may be operable to generate internal clocks dependent upon received data, and the generated internal clocks may enable the feedback and input circuits.

Energy efficient flip-flop with reduced setup time

A level shifter and integrated level shifter and metastability resolution flop circuit are disclosed. A circuit includes a generation circuit, in a first voltage domain, coupled to receive a logic signal via a single-ended input and configured to generate true and complementary values of the logic signal. The circuit further includes a storage circuit coupled to receive the true and complementary values of the logic signal from the generation circuit. The storage circuit is configured to store the true and complementary values of the logic signal. The storage circuit is in a second voltage domain. The circuit further includes an output circuit coupled to the storage circuit and configured to provide a differential output signal having true and complementary values corresponding to the true and complementary values of the logic signal. The circuit may be combined with a latch circuit coupled to receive the differential output signal.

Level shifter circuit optimized for metastability resolution and integrated level shifter and metastability resolution circuit

Embodiments of a logic path are disclosed that may allow for a reduction in switching power. The logic path may include a storage circuit, a comparison circuit, and a clock gating circuit. The storage circuit may be configured to store received data responsive to a local clock signal. The comparison circuit may be operable to compare the received data to data previously stored in the storage circuit. The clock gating circuit may be configured to generate the local clock signal dependent on a global clock signal, and de-activate the local clock signal dependent upon the results of the comparison performed by the comparison circuit.

Fine grain data-based clock gating

A process-tolerant large-swing sense amplifier with latching capability includes top-array and bottom-array access. The sense amplifier provides improved tolerance to process variation, reduces design complexity, reduces power consumption, and reduces the physical footprint of the circuit. In addition, the sense amplifier provides write-through functionality through the read data bus.

Process tolerant large-swing sense amplfier with latching capability

An apparatus and method of scanning a dual edge-triggered flip-flop with scan capability includes a first scan slave element capable of capturing data on a positive edge of a clock signal; and a second scan slave element capable of capturing data on a negative edge of the clock signal. An apparatus and method of scanning a dual edge-triggered flip-flop with scan capability includes a scan slave element capable of capturing data on either a positive edge or a negative edge of a clock signal; wherein a control signal determines whether the scan slave element captures data on the positive edge or negative edge of the clock signal.

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San Jose, CA, United States of America

Ha Pham