Samsung Electronics Co., Ltd.

Seoul National University

Ha-Jin Lim

Weon-hong Kim

Jong-Ho Lee

Moon-kyun Song

Dae-Kwon Joo

Jin-Ho Do

Hyung-Suk Jung

Dong-Suk Shin

Yun-Seok Kim

Gi-Gwan Park

Hyung-suk Jung

Moon-han Park

Pan-Kwi Park

Nae-in Lee

Young-sun Kim

Sung-Tae Kim

Jong-Cheol Lee

Jae-Eun Park

Hoi-Sung Chung

Jae-Hyun Yeo

Young-Geun Park

Gab-Jin Nam

Jong-Ho Yang

Hyeong-Joon Kim

Yun-Ki Choi

Cha-young Yoo

Min-Woo Song

Jae-hyoung Choi

Tae-Gyun Kim

Yong-Kuk Jeong

Min Joo Kim

Cha-Young Yoo

Dong-Hyun Roh

Kook-tae Kim

Tae-gyun Kim

Jong-Pyo Kim

Jong-Han Lee

Yun Seok Kim

Jeong-hyuk Yim

Jae-Hyoung Choi

Jun-Jung Kim

Jae-Sung Hur

Moon-Kyun Song

Jin-ho Do

Eun-Gon Kim

Joo-Won Lee

Jong-Min Jeon

Hye-Ri Hong

Sang-yub Ie

Hye-ri Hong

An image sensor includes a photoelectric converter in a pixel area of a substrate to generate photoelectrons in response to an incident light that is incident onto the pixel area, a signal generator on a first surface of the substrate in the pixel area to generate electric signals corresponding to image information of an object in accordance with the photoelectrons, and a pixel separation pattern penetrating through the substrate from the first surface of the substrate to a second surface of the substrate opposite to the first surface of the substrate, the pixel separation pattern including an insulation pattern having a refractive index smaller than that of the substrate and a metallic conductive pattern enclosed by the insulation pattern, and the pixel area being enclosed by the pixel separation pattern and isolated from a neighboring pixel area.

Image sensor with separation pattern and image sensor module including the same

An integrated circuit device includes a first gate stack formed on a first high dielectric layer and comprising a first work function adjustment metal containing structure and a second gate stack formed on a second high dielectric layer and comprising a second work function adjustment metal containing structure having an oxygen content that is greater than that of the first work function adjustment metal containing structure.

Integrated circuit device and method of manufacturing the same

A semiconductor device includes a semiconductor substrate comprising a group III element and a group V element, and a gate structure on the semiconductor substrate. The semiconductor substrate includes a first region which contacts a bottom surface of the gate structure and a second region which is disposed under the first region. The concentration of the group III element in the first region is lower than that of the group V element in the first region, and the concentration of the group III element in the second region is substantially equal to that of the group V element in the second region.

Semiconductor device and method of fabricating the same

Methods of manufacturing a semiconductor device are provided. The methods may include forming a fin-type active region protruding from a substrate and forming a gate insulating film covering a top surface and both sidewalls of the fin-type active region. The gate insulating film may include a high-k dielectric film. The methods may also include forming a metal-containing layer on the gate insulating film, forming a silicon capping layer containing hydrogen atoms on the metal-containing layer, removing a portion of the hydrogen atoms contained in the silicon capping layer, removing the silicon capping layer and at least a portion of the metal-containing layer, and forming a gate electrode on the gate insulating film. The gate electrode may cover the top surface and the both sidewalls of the fin-type active region.

Methods of manufacturing semiconductor devices

A semiconductor device includes a semiconductor substrate including a group III element and a group V element, and a gate structure on the semiconductor substrate. The semiconductor substrate includes a first region which contacts a bottom surface of the gate 5 structure and a second region which is disposed under the first region. The concentration of the group III element in the first region is lower than that of the group V element in the first region, and the concentration of the group III element in the second region is substantially equal to that of the group V element in the second region.

A method of fabricating a semiconductor device includes: forming an epitaxial layer on a semiconductor substrate; forming a capping layer having a first thickness on the epitaxial layer; and oxidizing the capping layer in an oxygen atmosphere to form a first gate dielectric layer having a second thickness.

Method of fabricating semiconductor device

Provided are a method of forming a dielectric and a method of fabricating a semiconductor device. The method includes forming a preliminary dielectric including Hf, O and an 'A' element on an underlying layer. The preliminary dielectric is formed in an amorphous structure or a mixed structure of an amorphous structure and an 'M' crystalline structure. The &#x201c;A&#x201d; element about 1 at % to about 5 at % of the total content of the &#x201c;A&#x201d; element and Hf in the preliminary dielectric. Through a nitridation process, nitrogen is added to the preliminary dielectric. The nitrogen-containing dielectric is changed into a dielectric having a &#x201c;T&#x201d; crystalline structure through a phase transition process, wherein the &#x201c;T&#x201d; crystalline structure is different from the &#x201c;M&#x201d; crystalline structure. An upper layer is formed on the &#x201c;T&#x201d; crystalline dielectric.

Method of forming a high-k crystalline dielectric

Semiconductor devices and methods of forming the semiconductor device are provided, the semiconductor devices including a first dielectric layer on a substrate, and a second dielectric layer on the first dielectric layer. The first dielectric layer has a carbon concentration lower than the second dielectric layer.

Semiconductor devices with dielectric layers

Methods of manufacturing a semiconductor device include forming a gate insulation layer including a high-k dielectric material on a substrate that is divided into a first region and a second region; forming a diffusion barrier layer including a first metal on a second portion of the gate insulation layer in the second region; forming a diffusion layer on the gate insulation layer and the diffusion barrier layer; and diffusing an element of the diffusion layer into a first portion of the gate insulation layer in the first region.

Semiconductor devices having a diffusion barrier layer and methods of manufacturing the same

A method of forming a semiconductor device includes forming a gate electrode and source/drain regions in a semiconductor substrate, forming a first capping nitride layer covering the gate electrode and the source/drain regions, the first capping nitride layer including a Si&#x2014;H rich SiN layer, annealing the semiconductor substrate having the first capping nitride layer, and removing the first capping nitride layer.

Method of forming semiconductor device using Si-H rich silicon nitride layer

Methods of manufacturing semiconductor devices include providing a substrate including a NMOS region and a PMOS region, implanting fluorine ions into an upper surface of the substrate, forming a first gate electrode of the NMOS region and a second gate electrode of the PMOS region on the substrate, forming a source region and a drain region in portions of the substrate, which are adjacent to two lateral surfaces of the first gate electrode and the second gate electrode, respectively, and performing a high-pressure heat-treatment process on an upper surface of the substrate by using non-oxidizing gas.

There is provided a method of manufacturing a semiconductor device. In the method, a gate insulation layer including a high-k dielectric material is formed on a substrate. An etch stop layer is formed on the gate insulation layer. A metal layer is formed on the etch stop layer. A hard mask including amorphous silicon is formed on the metal layer. The metal layer is patterned using the hard mask as an etching mask to form a metal layer pattern.

Method of patterning a semiconductor device with hard mask

Growing community of inventors

Seoul, South Korea

Ha-Jin Lim