Arm Limited

Håkan Lars-Göran Persson

Ian Rudolf Bratt

Jamshed Jalal

Andrew Brookfield Swaine

Bruce James Mathewson

Andrew Christopher Rose

Matthew Lucien Evans

Frederic Claude Marie Piry

Phanindra Kumar Mannava

Klas Magnus Bruce

Albin Pierrick Tonnerre

Antony John Harris

Daniel Adam Sara

Thomas James Cooksey

Vladimir Dolzhenko

Steven John Price

In response to determining circuitry determining that a portion of data to be sent to a recipient over an interconnect has a predetermined value, data sending circuitry performs data elision to: omit sending at least one data FLIT corresponding to the portion of data having the predetermined value; and send a data-elision-specifying FLIT specifying data-elision information indicating to the recipient that sending of the at least one data FLIT has been omitted and that the recipient can proceed assuming the portion of data has the predetermined value. The data-elision-specifying FLIT is a FLIT other than a write request FLIT for initiating a memory write transaction sequence. This helps to conserve data FLIT bandwidth for other data not having the predetermined value.

Data elision

A data processing system that comprises an encoder, and a communication system is disclosed. Compressed data produced by the encoder is decompressed to produce first decompressed data, and a first signature representative of the first decompressed data is generated. Compressed data that has been transferred by the communication system is decompressed to produce second decompressed data, and a second signature representative of the second decompressed data is generated. The first signature and the second signature are compared, and the comparison is used to determine whether an error has occurred.

Data processing systems

When storing data of an array of data in memory in a graphics processing system, respective memory regions are allocated for storing blocks of the data array, with the allocated region of memory for a block of the data array corresponding to a maximum possible size of the block of the data array when compressed, and being divided into a plurality of memory allocation sub-blocks, having at least one sub-block having a first, larger size and at least one sub-block having a second, smaller size. Blocks of the data array are compressed using a compression scheme, with each compressed block being stored in one or more of the sub-blocks of its allocated memory region.

Methods of and apparatus for storing data in memory in graphics processing systems

Apparatuses and methods are disclosed for performing data processing operations in main processing circuitry and delegating certain tasks to auxiliary processing circuitry. User-specified instructions executed by the main processing circuitry comprise a task dispatch specification specifying an indication of the auxiliary processing circuitry and multiple data words defining a delegated task comprising at least one virtual address indicator. In response to the task dispatch specification the main processing circuitry performs virtual-to-physical address translation with respect to the at least one virtual address indicator to derive at least one physical address indicator, and issues a task dispatch memory write transaction to the auxiliary processing circuitry comprises the indication of the auxiliary processing circuitry and the multiple data words, wherein the at least one virtual address indicator in the multiple data words is substituted by the at least one physical address indicator.

Task dispatch

Apparatuses and methods for address translation invalidation are provided. In an apparatus having address translation storage which stores merged address translation information for multiple address translation stages, a set of counters are provided to hold a set of counter values. Entries in the address translation storage are stored with identifiers of first and second counters selected from the set of counters in dependence on respective context information for a first stage and a second stage of address translation together with a counter value of each counter. In response to an invalidation request specifying a first or second addressing scheme invalidation context a counter of the set of counters is selected in dependence on the first or second addressing scheme invalidation context and its value is modified. Subsequently an entry in the address translation storage is determined to be invalid when either the first counter value does not match a current value of the first counter or the second counter value does not match a current value of the second counter.

Invalidation of entries in address translation storage

A data processing system includes a host processor that executes an operating system and an accelerator operable to process data under the control of the operating system executing on the host processor. The accelerator can be switched between a normal mode of operation and a protected mode of operation in which the side channel information that can be provided by the accelerator to the host processor is restricted. The data processing system also includes a mechanism for switching the accelerator from its normal mode of operation to the protected mode of operation, and from its protected mode of operation to the normal mode of operation.

A filter comprises interface circuitry, to intercept coherency protocol transactions exchanged between a master device comprising a first cache and an interconnect for managing coherency between the first cache and at least one other cache or other master device. The filter has filtering circuitry for filtering the coherency protocol transactions in dependence on memory access permission data defining which regions of an address space the master device is allowed to access.

Filtering coherency protocol transactions

A cache memory, such as a translation lookaside buffer cache, includes a plurality of blocks of bit storage circuitswhich can operate in either a first mode to store a plurality of shared-tagged data values having a shared tag, which his stored in a tag memory, or in a second mode to store a plurality of individual-tag data values and respective individual tags. The tag entries within the tag memory comprise the shared tag value for a given block operating in the first mode and a composite value for a given block operating in the second mode. The composite value includes a discriminator value indicative of the respective individual tags, such as a hash value or a Bloom filter value calculated in dependence upon the individual tags, using which potential matches with the individual tags may be identified from the discriminator value.

Cache memory

Interconnect circuitry and a method of operating the interconnect circuitry are provided, where the interconnect circuitry is suitable to couple at least two master devices to a memory, each comprising a local cache. Any access to the memory mediated by the interconnect circuitry is policed by a memory protection controller situated between the interconnect circuitry and the memory. The interconnect circuitry modifies a coherency type associated with a memory transaction received from one of the master devices to a type which ensures that when a modified version of a copy of a transaction target specified by the issuing master device is stored in a local cache of another master device an access to the transaction target in the memory must take place and therefore must be policed by the memory protection controller.

Growing community of inventors

Bjärred, Sweden

Håkan Lars-Göran Persson