Advanced Micro Devices Corporation

Globalfoundries Inc.

H S Ramagopal

Rajiv M Hattangadi

Thang M Tran

James K Pickett

Muralidharan Santharaman Chinnakonda

An apparatus for performing speculative stores is provided. The apparatus reads the original data from a cache line being updated by a speculative store, storing the original data in a restore buffer. The speculative store data is then stored into the affected cache line. Should the speculative store later be canceled, the original data may be read from the restore buffer and stored into the affected cache line. The cache line is thereby returned to a pre-store state. In one embodiment, the cache is configured into banks. The data read and restored comprises the data from one of the banks which comprise the affected cache line. Instead of forwarding store data to subsequent load memory accesses, the store is speculatively performed to the data cache and the loads may subsequently access the data cache. Dependency checking between loads and stores prior to the speculative performance of the store may stall the load memory access until the corresponding store memory access has been performed. Similar functionality to forwarding of store data is obtained through the performance of load memory accesses to the data cache. Additionally, speculative load memory accesses which are partially overlapped by a prior speculative store memory access may be performed more efficiently.

Apparatus and method for performing speculative stores

Apparatus and method performing speculative stores

A load/store buffer is provided which allows both load memory operations and store memory operations to be stored within it. Because each storage location may contain either a load or a store memory operation, the number of available storage locations for load memory operations is maximally the number of storage locations in the entire buffer. Similarly, the number of available storage locations for store memory operations is maximally the number of storage locations in the entire buffer. This invention improves use of silicon area for load and store buffers by implementing, in a smaller area, a performance-equivalent alternative to the separate load and store buffer approach previously used in many superscalar microprocessors.

Superscalar microprocessor load/store unit employing a unified buffer

A load/store buffer is provided which allows both load memory operations and store memory operations to be stored within it. Memory operations are selected from the load/store buffer for access to the data cache, including cases where the memory operation selected is subsequent in program order to a memory operation which is known to miss the data cache and is stored in the buffer. In this way, other memory operations that may be waiting for an opportunity to access the data cache may make such accesses, while the memory operations that have missed await an opportunity to make a main memory request. Memory operations that have missed are indicated by a miss bit being set, so that the mechanism which selects memory operations to access the data cache may ignore them until they become non-speculative.

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Austin, TX, United States of America

H S Ramagopal