Creative Integrated Systems, Inc.

Rocoh Company, Ltd.

Creative Integrated Ststems, Inc.

H Nakanishi

Clarence W Padgett

James A Komarek

Jack L Minney

Scott B Tanner

Keiji Fukumura

Motohiro Oishi

Shin-ichi Kojima

An input receiver circuit in a read-only memory is provided with a feedback to control hysteresis. A second stage and an additional output is added to the receiver. Switching circuit noise from inside of the read-only memory is isolated by the added state and outputs, and cannot be fed back into the receiver circuit to affect the detection of the TTL voltage levels. Use of wide and long FET sizes minimizes the manufacture related variations in the input receiver switching levels.

NMOS input receiver circuit

A memory precharge voltage, VPC, is provided which tracks changes in the high voltage supply, VDD, according to a measured degree, which maintains a precharge voltage notwithstanding transient loads which may tend to draw the precharge voltage down, and which maintains the precharge voltage at the operating level notwithstanding the fact that the precharge generator is substantially turned off during a power down condition. The precharge voltage, VPC, is then used as the controlling input signal to a circuit which it generates and an internal control voltage, MLC, used to drive small pull-up current FETs coupled to the bit lines in the ROM core. The internal control signal MLC is generated to track the discharge current in a bit line within the memory core, to track VPC, and to be maintained at its operating voltage level even when the MLC current is substantially turned off during a power down condition.

VLSI memory circuit

The invention is a control circuit for controlling an interrupt driver coupled to the data outputs of a memory having address transition detection circuitry. The memory is operable in a standby and an active memory mode in sequential memory cycles. The control circuit comprises an output enable latch circuit which provides internal memory signal of whether the memory was operating in the standby or active mode during a previous memory cycle and a data latch circuit which provides an internal memory signal of whether a new read cycle is beginning within the memory. The data latch circuit is reset when address detection has occurred within the memory. A logic circuit combines an output of the data latch circuit, which is indicative of a memory read cycle, with an output of the output enable latch circuit, which is indicative of whether the prior memory cycle was standby or active. The logic circuit generates an output enable signal, OE, which is coupled to the output drivers of the memory to control float of the output drivers. As a result, a smooth transition from old data to new data is obtained, and system data bus contention in transitions from standby to active modes is eliminated.

Output driver control for ROM and RAM devices

The invention is a dynamic ROM design for read cycle interrupts. The clock scheme of the improved memory generates a primary start clock. The relatively long pulse time of START when high is provided for setting the latches. This pulse duration is controlled by PCOK or OWDN one shot circuit. When an address interrupt occurs early in the read cycle, while PCOK or OWDN clock is low, and START is high, these one shot circuits provide a simple means of restarting the cycle by continuing the precharge phase of the cycle with no effect on most of the secondary clocks in the memory. Only those clocks relating to the new address inputs are effected by the early interrupt. This results in less power dissipation and less bus noise.

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Hyougo, Japan

H Nakanishi