Motorola Corporation

H Ming Liaw

Mamoru Tomozane

Bertrand Francis Cambou

Robert W Helda, Deceased

William C Dunn

Raymond Mervin Roop

Juergen A Foerstner

Ljubisa Ristic

Charles J Varker

By Cynthia Hazeltine, Executor

By Cynthia Halextine, Personal Representative

A SIMOX structure having a reduced number of defects is formed by performing a two step anneal. In one embodiment, a conventional anneal is followed by an H.sub.2 /Si anneal. The conventional anneal first densifies the buried oxide layer in order to make the oxide less reactive with hydrogen. The H.sub.2 /Si anneal forms a quasi-equilibrium at the superficial semiconductor layer surface, thus there is no etching of the silicon surface and there is only a negligible amount of silicon deposition. The H.sub.2 reacts with the oxide precipitates and dissolves them. In a second embodiment the two step anneal comprises a low temperature H.sub.2 anneal followed by a conventional anneal. At low temperature, H.sub.2 can diffuse through silicon, but is much less reactive. Thus, etching of the superficial silicon and silicon dioxide buried layer is minimal. The conventional anneal is at a higher temperature, thus H.sub.2 can react with the oxygen precipitates to remove them.

Method of forming a SIMOX structure

A non-silicon substrate is bonded to a silicon substrate with a stress-relief layer between the non-silicon substrate and the silicon substrate. The stress-relief layer reduces the stress between the non-silicon substrate and the silicon substrate. The stress is created by the difference in the thermal expansion coefficients of the two materials. The stress-relief layer may be a low melting point metal, a semiconductor layer having its thermal expansion coefficient close to the thermal expansion coefficient of the non-silicon substrate. The silicon substrate and/or the non-silicon substrate may have a silicon dioxide layer formed thereon such that the silicon dioxide layer is adjacent to the stress-relief layer.

Non-silicon and silicon bonded structure and method of manufacture

A structure is provided to integrate bulk structure resonators into a monolithic integrated circuit chip. The chip also contains the remaining circuit components (17, 21, 24) required for the desired system function. Micromachining techniques are used to fabricate both support and a cavity (11, 27, 28) which allows mechanical vibration without interference. Alternative embodiments incorporate the use of non-piezoelectric mechanical resonators (14), quartz crystal resonators (18) and thin film piezoelectric resonators (22). Each type of resonator is used for the range of frequencies to which it is suited, providing a family of monolithic resonators capable of being used with integrated circuits having operating frequencies from a few hundred hertz to over 500 Mhz.

Monolithic circuit with integrated bulk structure resonator

A thick buried insulating layer is formed by employing a multiple semiconductor layer growth/implant/anneal cycle. A first buried insulating layer is formed in a semiconductor substrate by implanting a dopant which reacts with the substrate to form an insulating layer and then annealing the substrate. Subsequently, a thin semiconductor layer is grown on the surface of the substrate. This is followed by a second implantation of the dopant which reacts with the substrate to form an insulating layer and an anneal to form a second buried insulating layer. The two buried insulating layers may be continuous to form a single, thick buried insulating layer or may be discontinuous to form two buried insulating layers separated by a semiconductor layer. The cycle may be repeated until a desirable thickness of the buried insulating layer is achieved or until a desirable number of buried insulating layers are formed.

Method of fabricating buried insulating layers

A dielectric isolated area is formed by bonding a first and a second wafer. A first wafer having a first and a second major surface is provided. A second wafer having a first and a second major surface is then provided. Trenches are formed in the first surface of the second wafer. Subsequently, a dielectric layer which can be planarized is formed on the surface of the second wafer having trenches formed therein. The first and second wafers are then bonded so that the dielectric layer and the first surface of the first wafer are bonded to each other. A portion of the second surface of the second wafer is then removed down to at least the bottom of each trench.

Method of fabricating a dielectric isolated area

Silicon and non-silicon semiconductor devices are fabricated on a single chip by bonding a silicon wafer to a non-silicon semiconductor substate. Portions of the non-silicon semiconductor substrate are selectively etched to expose the silicon wafer. Semiconductor devices may then be formed in the silicon wafer and on the non-silicon semiconductor substrate. Alternatively, selective epitaxial silicon may be grown where the non-silicon semiconductor substrate was removed. In another embodiment, a non-silicon semiconductor substrate having wells formed therein is bonded to a silicon wafer. The non-silicon semiconductor substrate is then polished until openings are provided to the silicon wafer. Further processing is carried out as described above.

Method of fabricating integrated silicon and non-silicon semiconductor

An improved method of fabricating a defect-free semiconductor layer and a semiconductor on insulator structure is provided by forming an isoelectronically doped semiconductor layer between a substrate and an semiconductor layer. The isoelectronic dopant atoms are different in atomic size than the atoms of the semiconductor material, thus misfit dislocations are created at the interface of the isoelectronically doped semiconductor layer due to lattice mismatch. Impurities and defects are not only gettered to the misfit dislocation sites, but are also prevented from propagating to the epitaxial layer. These misfit dislocations are thermally stable and are confined in a plane parallel to the interfaces of the isoelectronically doped semiconductor layer, thus very effective gettering agents. If the isoelectroncially doped semiconductor layer us also a heavily doped buried layer, no misfit dislocations are desired because the buried layer is an active device layer. In this case the isoelectronic dopant atoms may offset the non-isoelectronic dopant atoms in atomic size, thus no misfit dislocations are formed.

Method of forming a defect-free semiconductor layer on insulator

A melt recharge method is disclosed which uses a self-actuated charge container open at one end except for deformable support members which are positioned to support the charge material. The support members are formed of a material which has sufficient rigidity at room temperature to support the charge material but which when heated above its annealing temperature loses its rigidity and can no longer support the charge material which therefore falls into the existing melt. Upon cooling, the support members regain their rigidity and can be reformed for reuse.

Melt recharge method

A self-actuated charge container is open at one end except for deformable support members which are positioned to support the charge material. The support members are formed of a material which has sufficient rigidity at room temperature to support the charge material but which when heated above its annealing temperature loses its rigidity and can no longer support the charge material which therefore falls into the existing melt. Upon cooling, the support members regain their rigidity and can be reformed for reuse.

Melt recharge apparatus

A combined method for purifying silicon and growing single crystals. A multiple step process is disclosed by which metallurgical grade silicon is purified and converted into a high quality monocrystalline silicon ingot. Each of the steps in the process is designed to remove specific impurities and thus improve the electrical quality of the silicon material. First, the insoluble slag and high segregation coefficient impurities are removed. Soluble impurities are then removed by a reactive gas step, and by a liquid-liquid extraction step using reactive metallic oxides or an oxide solvent. The remaining impurities are removed by segregation during freezing by pulling an ingot from a portion of the molten metallurgical grade silicon. The ingot so formed is then used to charge a second crystal puller. One or more of the previous purifying steps can then be repeated for the charge of the second crystal puller and an ingot of improved purity can be pulled from the melt of the second puller. In like manner, third and successive reiterations of the process can be used to obtain silicon of the desired purity and crystal quality.

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Scottsdale, AZ, United States of America

H Ming Liaw