Advanced Micro Devices Corporation

Tokyo Electron Limited

Micron Technology Incorporated

Other

Cypress Semiconductor Corporation

H Jim Fulford

Mark I Gardner

Derick J Wristers

Robert Louis Dawson

Mark W Michael

Fred N Hause

Frederick N Hause

William S Brennan

Basab Bandyopadhyay

Bradley T Moore

Charles E May

Anton J deVillers

Partha Mukhopadhyay

Jon D Cheek

Lars W Liebmann

Daniel Chanemougame

Jeffrey Smith

Vladimir Mikhalev

Dim-Lee Kwong

Anthony R Schepis

Michael A Smith

James F Buller

Thomas E Spikes, Jr

Daniel J Fulford

Homi E Nariman

Zia Alan Shafi

Puneet Sharma

Daniel Kadosh

Anthony John Toprac

Robert Daniel Clark

Thomas J Sonderman

Craig William Christian

Jack C Lee

Derrick J Wristers

Said N Ghneim

Yongjun Jeff Hu

Gordon A Haller

Kandabara N Tapily

Mark C Gilmer

Jie Sun

Brett D Lowe

William Jarrett Campbell

James Mathew

Christopher H Raeder

John J Bush

Lequn Jennifer Liu

Yunjun Ho

Zhaoli Sun

Dirk J Wristers

Arya Bhattacherjee

Antoine Khoueir

Michael J Allen

Subhadeep Kal

Sey-Ping Sun

Jeremy Sam Lansford

Robert Paiz

Allen Lewis Evans

David C Conklin

Andrew Weloth

Mike Smith

Dim Lee Kwong

Anton J Devilliers

Jay J Seaton

Subhash Srinivas Pidaparthi

Randy Blair

Steven C Hall

A semiconductor device includes a first transistor and a second transistor. The first transistor includes a first channel structure positioned over a substrate, first source/drain (S/D) regions positioned on ends of the first channel structure, and a first gate structure disposed all around the first channel structure. The second transistor includes a second channel structure positioned over the first channel structure, second S/D regions positioned on ends of the second channel structure, and a second gate structure disposed all around the second channel structure. The second channel structure has a smaller dimension than the first channel structure in a horizontal direction substantially parallel to a working surface of the substrate.

Compact 3D design and connections with optimum 3D transistor stacking

Systems and methods are provided herein for determining the planarity of a semiconductor wafer. The systems and methods described herein utilize a capacitive measurement tool to detect and characterize the bow of a semiconductor wafer. The capacitive measurement tool disclosed herein utilizes a non-contact, capacitive sensor unit to measure wafer bow. Unlike conventional capacitive sensing techniques used to measure wafer bow, the capacitive sensor unit disclosed herein uses a plurality of electrodes for simultaneously obtaining a plurality of capacitance measurements from the wafer at various locations on the wafer surface. By including a plurality of electrodes within the capacitive sensor unit, the techniques described herein increase the amount of data collected across the wafer surface at any given time to improve the throughput and measurement accuracy of the capacitive measurement tool.

Contactless capacitive measurement tool with improved throughput and accuracy

A semiconductor device includes a memory cell unit positioned over a substrate. The memory cell unit includes a transistor and a capacitor. The capacitor includes an inner conductor, a capacitor dielectric all around the inner conductor, an outer conductor all around the capacitor dielectric, and dielectric support structures below the inner conductor. The capacitor is elongated in a length direction parallel to a working surface of the substrate, and the dielectric support structures are spaced along the length direction. The transistor includes a channel structure, a gate structure all around the channel structure, and source/drain (S/D) regions on opposing ends of the channel structure.

3D horizontal memory cell with sequential 3D vertical stacking

Aspects of the present disclosure provide a bonding device for bonding two wafers. For example, the bonding device can include a first bonding chuck and a second bonding chuck. The first bonding chuck can have a first bonding head for a first wafer to be mounted thereon. The second bonding chuck can have a plurality of second bonding heads for a second wafer to be mounted thereon. The second bonding heads can be controlled individually to apply local pressures onto the second wafer to move the second wafer toward the first wafer to bond the second wafer to the first wafer, the local pressures corresponding to bow measurement of the first wafer and the second wafer.

3D multiple location compressing bonded arm for advanced integration

One or more 3D transistor structures that use one or more 2D materials as transistor channels along with methods for fabricating the same are disclosed. A 3D transistor can include a first carrier nanosheet at least partially surrounded by a first 2D material and a second carrier nanosheet at least partially surrounded by a second 2D material. The transistor can include a first source/drain structure in electrical contact with a first end of the first 2D material and a first end of the second 2D material. The transistor can include a second source/drain structure in electrical contact with a second end of the first 2D material and a second end of the second 2D material. The transistor can include a gate structure at least partially surrounding the first 2D material and the second 2D material.

2D material to integrate 3D horizontal nanosheets using a carrier nanosheet

A device including one or more transistors with nano sheets stacked along a vertical direction, and a method of fabricating the device are disclosed herein. In some embodiments, a device includes a transistor structure including at least a first dielectric nano sheet and a second dielectric nano sheet. The first dielectric nano sheet and the second dielectric nano sheet may extend parallel to a substrate. The second dielectric nano sheet may be disposed above the first dielectric nano sheet. The transistor may include a first source/drain structure coupled to a first end of the first dielectric nano sheet and a first end of the second dielectric nano sheet, and a second source/drain structure coupled to a second end of the first dielectric nano sheet and a second end of the second dielectric nano sheet.

Methods for forming high performance three dimensionally stacked transistors based on dielectric nano sheets

Methods for the manufacture of semiconductor devices constructed with three-dimensional (3D) horizontal nano sheets with high mobility two-dimensional (2D) material channels are disclosed. Aspects can include forming a semiconductor material; selectively forming a seed material around the bridge; selectively forming a two-dimensional (2D) material around the seed material; forming an active gate around a central portion of the 2D material thereby exposing end portions of the 2D material; and growing source/drain structures coupled to the end portions of the 2D material, respectively.

Epitaxial semiconductor 3D horizontal nano sheet with high mobility 2D material channel

Systems and methods for manufacturing semiconductor devices. The system can include a semiconductor device. The semiconductor device can include a semiconductor shell that extends along a vertical direction. The semiconductor device can include a first metal structure surrounded by a lower portion of the semiconductor shell. The semiconductor device can include a dielectric structure above the first metal structure. The semiconductor device can include a second metal structure through the dielectric structure.

3D device with a plurality of core wiring layout architecture

Aspects of the present disclosure provide 3D semiconductor structures and methods for fabricating the same. For example, the method can include forming a first multilayer stack over a substrate, forming a second multilayer stack over the first multilayer stack, forming a first opening through the first and second multilayer stack until uncovering a top surface of the substrate, forming in the first opening a first vertical field-effect transistor (VFET) over the substrate, and forming in the first opening a second VFET over the first VFET. The first VFET can include a first channel having a first length corresponding to a first thickness of a first layer of the first multilayer stack. The second VFET can include a second channel having a second length corresponding to a second thickness of a second layer of the second multilayer stack. The second thickness can be different from the first thickness.

Plurality of devices in adjacent 3D stacks in different circuit locations

A method for manufacturing a semiconductor device is described. The method includes forming a first complementary field effect transistor. The first complementary field effect transistor has a first transistor of a first conductivity type, and a second transistor of a second conductivity above the first transistor. The first transistor includes a first gate electrode, a first channel above the first gate electrode, and first source and drain contacts above the first channel layer. The second transistor includes a second gate electrode, a second channel, and second source and drain contacts. The second channel is disposed between the second source and drain contacts and the second gate electrode. At least one of the first channel or the second channel includes a two-dimensional semiconductor material or an oxide semiconductor.

High performance new channel materials precision aligned 3D CFET device architecture

Semiconductor devices and corresponding methods of manufacturing the same are disclosed. For example, a plurality of first semiconductor channels vertically spaced from one another and a plurality of second semiconductor channels vertically spaced from one another can be provided. The plurality of first semiconductor channels each have a first sidewall in contact with a first dielectric structure and the plurality of second semiconductor channels each have a first sidewall in contact with a second dielectric structure. A cavity can be formed between the first sidewalls of the plurality of first and second semiconductor channels. Gate structures can be formed around at least a top surface, a bottom surface, and a second sidewall of the first and second semiconductor channels.

3D isolation of a segmentated 3D nanosheet channel region

A method includes forming a fin structure over a substrate, the fin structure including alternating first semiconductor layers and second semiconductor layers stacked along a vertical direction; forming a dummy gate structure over the fin structure; selectively depositing an outer spacer layer on the dummy gate structure; performing a plasma doping process to form source/drain regions in each second semiconductor layer adjacent the dummy gate structure, where a portion of each second semiconductor layer interposing between the source/drain regions defines a channel region; forming a dielectric layer over the fin structure; removing the dummy gate structure to form a gate trench in the dielectric layer; selectively removing the first semiconductor layers to form openings interleaved with the second semiconductor layers; and forming a metal gate structure to fill the gate trench and the openings.

Semiconductor devices and methods of manufacturing thereof

A semiconductor device includes a stack of dynamic random access memory (DRAM) cell units over a substrate in a vertical direction. At least one DRAM cell unit includes a transistor and a capacitor. The capacitor includes a first metal layer, a capacitor dielectric layer on the first metal layer, and a second metal layer on the capacitor dielectric layer. The capacitor is elongated in a horizontal direction. The first metal layer has a first end and a second end in the horizontal direction. The transistor includes a channel structure, and a gate structure on the channel structure. The second metal layer extends in the horizontal direction beyond the first end of the first metal layer to form a drain region and a source region of the transistor. A common ground structure is configured to electrically connect to a plurality of first metal layers on respective second ends.

3D memory with cell stacking using an in-situ capacitor stack

A semiconductor device includes a stack of layers defining a sidewall surface and comprising source and drain layers. A channel structure extends through the stack of layers, is oriented in a vertical direction perpendicular to a main surface of the stack of layers, and is configured to have a current flow path in the vertical direction. The channel structure includes a two-dimensional (2D) semiconductor material. A core structure is positioned inside and surrounded by the channel structure, and a gate structure surrounds at least part of the channel structure.

3D semiconductor device with 2D semiconductor material and method of forming the same

Example implementations can include a semiconductor device with a first seed layer including a first material and having a planar structure, the first material having a two-dimensional structure, a first device layer including a second material and disposed over a first surface of the first seed layer, the second material having a crystallized structure, and a second device layer including the second material and disposed over a second surface of the first seed layer opposite to the first surface of the first seed layer.

Semiconductor devices with crystallized channel regions and methods of manufacturing thereof

Growing community of inventors

Orlando, FL, United States of America

H Jim Fulford