International Business Machines Corporation

H Bernhard Pogge

Roy Rongqing Yu

Chandrika Prasad

Howard L Kalter

Johann Greschner

Chandrasekhar Narayan

Michel Despont

Peter Vettiger

Donald Lawrence Wheater

Ute Drechsler

Bijan Davari

Joseph Adam Aboaf

Raymond J Rosner

George S Prokop

Robert W Broadie

Burton J Masters

Siegfried R Mader

Subramania S Iyer

Edward M Hull

David V Horak

Steven J Holmes

Toshiharu Furukawa

Steven H Voldman

Mark Charles Hakey

Mukta G Farooq

Edmund Juris Sprogis

Wesley Charles Natzle

Roger Allan Quon

Christopher P Ausschnitt

Thomas Edward Lombardi

William Francis Landers

Ka Hing Fung

Hai Pham Longworth

Jasvir Singh Jaspal

Kerry L Batdorf

A system and method comprises depositing a dielectric layer on a substrate and depositing a metal layer on the dielectric layer. The system and method further includes depositing a high temperature diffusion barrier metal cap on the metal layer. The system and method further includes depositing a second dielectric layer on the high temperature diffusion barrier metal cap and the first dielectric layer, and etching a via into the second dielectric layer, such that the high temperature diffusion barrier metal cap is exposed. The system and method further includes depositing an under bump metallurgy in the via, and forming a C4 ball on the under bump metallurgy layer.

Structure and method to improve current-carrying capabilities of C4 joints

A vertical wafer-to-wafer interconnect structure is provided in which a first wafer and a second wafer are mated by way of metal studs that extend from a surface of the first wafer. The metal studs extend from the surface of the first wafer into a corresponding through via of the second wafer. A polyimide coating is present in the through via on mated surfaces of the first and second wafers and on another surface of the second wafer not mated to the first wafer, thus the metal studs provide a continuous metal path from the first wafer through the second wafer. Since only metal studs for the vertical connection are used, no alpha radiation is generated by the metal studs.

Metal filled through via structure for providing vertical wafer-to-wafer interconnection

A metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrate. The substrate is then thinned at the bottom surface thereof to expose the bottom of the feature, to form a conducting through-via. The substrate may comprise a chip having a device (e.g. DRAM) fabricated therein. The process therefore permits vertical integration with a second chip (e.g. a PE chip). The plate may be a wafer attached to the substrate using a vertical stud/via interconnection. The substrate and plate may each have devices fabricated therein, so that the process provides vertical wafer-level integration of the devices.

Chip and wafer integration process using vertical connections

A process is described for semiconductor device integration at chip level or wafer level, in which vertical connections are formed through a substrate. A metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrate. The substrate is then thinned at the bottom surface thereof to expose the bottom of the feature, to form a conducting through-via. The substrate may comprise a chip having a device (e.g. DRAM) fabricated therein. The process therefore permits vertical integration with a second chip (e.g. a PE chip). The plate may be a wafer attached to the substrate using a vertical stud/via interconnection. The substrate and plate may each have devices fabricated therein, so that the process provides vertical wafer-level integration of the devices.

A method is described for fabricating a three-dimensional integrated device including a plurality of vertically stacked and interconnected wafers. Wafers () are bonded together using bonding layers () of thermoplastic material such as polyimide; electrical connections are realized by vias () in the wafers connected to studs (). The studs connect to openings () having a lateral dimension larger than that of the vias at the front surfaces of the wafers. Furthermore, the vias in the respective wafers need not extend vertically from the front surface to the back surface of the wafers. A conducting body () provided in the wafer beneath the device region and extending laterally, may connect the via with the matallized opening () in the back surface. Accordingly, the conducting path through the wafer may be led underneath the devices thereof. Additional connections may be made between openings () and studs () to form vertical heat conduction pathways between the wafers.

Three-dimensional device fabrication method

A method of fabricating a through via connection useful in providing a vertical wafer-to-wafer interconnect structure is provided as well as the vertical interconnect structure that is formed by this method. The method of the present invention using only a metal stud for the vertical connection therefore no alpha radiation is generated by the metal stud. The method of the present invention includes an inserting step, a heating step, a thinning step and backside processing.

A vertically integrated structure includes a micro-electromechanical system (MEMS) and a chip for delivering signals to the MEMS. The structure includes a metal stud connecting a surface of the chip and the MEMS; the MEMS has an anchor portion having a conducting pad on an underside thereof contacting the metal stud. The MEMS is spaced from the chip by a distance corresponding to a height of the metal stud, and the MEMS includes a doped region in contact with the conducting pad. In particular, the MEMS may include a cantilever structure, with the end portion including a tip extending in the vertical direction. A support structure (e.g. of polyimide) may surround the metal stud and contact both the underside of the MEMS and the surface of the chip. A temporary carrier plate is used to facilitate handling of the MEMS and alignment to the chip.

Three-dimensional integrated CMOS-MEMS device and process for making the same

A structure and method are provided for dissipating heat from a semiconductor device chip. A first layer of a dielectric material (e.g. polyimide) is formed on a front side of a heat spreader (typically Si). A plurality of openings are formed through this first layer; the openings are filled with metal (typically Cu), thereby forming metal studs extending through the first layer. A second layer of metal is formed on the backside of the device chip. The first layer and the second layer are then bonded in a bonding process, thereby forming a bonding layer where the metal studs contact the second layer. The bonding layer thus provides a thermal conducting path from the chip to the heat spreader.

Method and device for heat dissipation in semiconductor modules

A semiconductor device structure including fine-pitch connections between chips is fabricated using stud/via matching structures. The stud and via are aligned and connected, thereby permitting fine-pitch chip placement and electrical interconnections. A chip support is then attached to the device. A temporary chip alignment structure includes a transparent plate exposed to ablating radiation; the plate is then detached and removed. This method permits interconnection of multiple chips (generally with different sizes, architectures and functions) at close proximity and with very high wiring density. The device may include passive components located on separate chips, so that the device includes chips with and without active devices.

Process for making fine pitch connections between devices and structure made by the process

A method is described for forming an integrated structure, including a semiconductor device and connectors for connecting to a motherboard. A first layer is formed on a plate transparent to ablating radiation, and a second layer on the semiconductor device. The first layer has a first set of conductors connecting to bonding pads, which are spaced with a first spacing distance in accordance with a required spacing of connections to the motherboard. The second layer has a second set of conductors connecting to the semiconductor device. The first layer and second layer are connected using a stud/via connectors having spacing less than that of the bonding pads. The semiconductor device is thus attached to the first layer, and the first set and second set of conductors are connected through the studs. The interface between the first layer and the plate is ablated by ablating radiation transmitted through the plate, thereby detaching the plate. The connector structures are then attached to the bonding pads. This method permits fabrication of a high-density packaged device with reduced cost.

Method of fabricating integrated electronic chip with an interconnect device

A vertically integrated structure includes a micro-electromechanical system (MEMS) and a chip for delivering signals to the MEMS. The MEMS has an anchor portion having a conductor therethrough, by which it is connected to a substrate. The chip is attached to the MEMS substrate in a direction normal to the substrate surface, so as to make a conductive path from the chip to the MEMS. The chip may be attached by bonding the conductor to C4 metal pads formed on the chip, or by bonding the conductor to metal studs on the chip. The MEMS substrate may be thinned before attachment to the chip, or may be removed from the underside of the MEMS. A temporary carrier plate is used to facilitate handling of the MEMS and alignment to the chip.

Large area chip functionality is tested at an intermediate level in the manufacturing process. A process sequence is implemented in which a layer of insulator material is deposited over the chip. This layer is then processed to selectively open areas over existing vias which are to be used for chip level testing. The other vias remain covered with insulator. A sacrificial metal level is then deposited on the insulator layer and patterned to create adequately large test pad areas connected to exposed vias. This metal layer and the insulator layer covering the other buried vias are removed after testing to re-establish the full via set. As an extension to this basic test process, test circuits can be formed around or beside the chip to be tested in the kerf areas separating the chip from other chips on the semiconductor wafer. Connections to the test circuits is with a sacrificial metal layer over an insulator layer. The sacrificial metal layer and insulator layer are removed after testing. The test circuits are scribed off in the process of separating the chips after back end of line processing is completed.

Method for chip testing

A process is described for integrating an optoelectronic chip and a driver chip on a substrate, in which a waveguide is built into the substrate and the chips are joined to the substrate using a stud/via alignment technique. The waveguide structure includes a reflector and a channel for transmitting light emitted by the optoelectronic chip. A stud formed on the substrate is aligned to a via formed in a layer on the chip, aligning the chip so that the light reaches the reflector and enters the waveguide. A driver chip may be mounted on the substrate in close proximity to the optoelectronic chip.

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Hopewell Junction, NY, United States of America

H Bernhard Pogge