Fujitsu Corporation

H Anders Kristensson

Nikola Nedovic

William Warren Walker

Nestor Tzartzanis

In one embodiment, a circuit includes a voltage-controlled oscillator (VCO) configured to generate k first clock signals that each have a first phase based on a charge-pump control voltage signal; one or more phase interpolators (PIs) configured to receive the k first clock signals and one or more first feedback controls signals and generate m second clock signals that each have a second phase based on the k first clock signals and the one or more first feedback control signals; a first phase detector (PD) configured to receive the m second clock signals and generate the one or more first feedback control signals based on the m second clock signals; a second PD configured to generate one or more second feedback control signals based on the m second clock signals; and a charge pump configured to output the charge-pump control voltage signal based on the second feedback control signals.

Clock and data recovery (CDR) using phase interpolation

In one embodiment, a circuit includes a first circuit input for receiving a first input signal having a first phase; a second circuit input for receiving a second input signal having a second phase; a circuit output for outputting a circuit output signal; a first mixer cell comprising a first mixer cell input, a second mixer cell input, and a first mixer cell output; and a second mixer cell comprising a third mixer cell input, a fourth mixer cell input, and a second mixer cell output. The first circuit input is connected to the first and second mixer cell inputs, the second circuit input is connected to the second and fourth mixer cell inputs, and the first and second mixer cell outputs are combined to provide the circuit output. The current of the circuit output signal is proportional to a phase offset between the first and second phases.

Symmetric phase detector

In one embodiment, a circuit includes a first circuit input for receiving a first reference signal having a first phase; a second circuit input for receiving a second reference signal having a second phase; a third circuit input for receiving a target phase signal; a circuit output for outputting an output signal; a first multiplying mixer cell (MMC) comprising a first MMC input, a second MMC input, and a first MMC output; a second MMC comprising a third MMC input, a fourth MMC input, and a second MMC output. In an example embodiment, the first circuit input is connected to the first MMC input; the second circuit input is connected to the third MMC input; the third circuit input is connected to the second MMC input and the fourth MMC input; the first MMC output and the second MMC output are combined with each other to provide the circuit output; and the output signal, when present, represents an error signal that is proportional to a phase difference between a phase of the target phase signal and an average of the first and second phases.

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Los Gatos, CA, United States of America

H Anders Kristensson