Samsung Electronics Co., Ltd.

Gyuseok Choe

Youngmin Lee

Soongmann Shin

Ikkyun Park

Myungsub Shin

Changjun Lee

Seongyong Jang

Seongwan Hong

Jinmyung Yoon

Seongheum Baik

A storage device and an operating method of the same are disclosed. The storage device includes a memory controller and a non-volatile memory, wherein the memory controller is configured to calculate a number of zones, which are spaces allocated to logical addresses, based on a cell area size of first storage areas of the non-volatile memory, and provide the number of zones to a host, is configured to generate multiple zones of a number within the calculated number of zones, and to map a logical address of each zone to a physical address of at least one of the first storage areas, and is configured to, in response to a first write request from the host, write data included in the first write request into first storage areas corresponding to a zone indicated by the first write request.

Storage device with variable cell area size and operating method thereof

An operating method of a storage device, including a core and a memory, includes receiving a first processing code configured to enable execution of a first task and storing the first processing code in a first logical unit separately allocated in the memory for near-data processing (NDP), in response to a write command received from a host device, activating the core for executing the first processing code, in response to an activation command received from the host device, and executing the first task by using the core, in response to an execution command received from the host device.

Storage device for executing processing code and operating method of the storage device

An operating method of a memory system including a memory device including a plurality of memory chips is provided. The operating method includes setting a parameter indicating a number of the memory chips allowed to operate in parallel for each of a plurality of operation statuses, based on information about power consumption of each of the plurality of operation statuses of a memory chip among the memory chips; obtaining information about an operation status of each of the plurality of memory chips; and scheduling data access across a plurality of channels respectively corresponding to the plurality of memory chips, based on the parameter and the information about the operation status of each of the plurality of memory chips.

Memory controller, memory system and operating method of the memory system using a channel arbitration circuit

Memory controller, memory system and operating method of the memory system for scheduling data access across channels of memory chips within the memory system

Growing community of inventors

Hwaseong-si, South Korea

Gyuseok Choe