Skhynix Inc.

Gyu Tae Park

Young Ouk Kim

Young Suk Seo

Jin Il Chung

Young Jae An

A clock generating circuit includes a first division circuit and a second division circuit. The first division circuit is configured to generate a first group of internal clock signals by dividing a clock signal. The second division circuit is configured to generate a second group of internal clock signals by dividing a delayed clock signal, the delayed clock signal generated by an internal circuit delaying the clock signal. An operation timing of the second division circuit can be adjusted based on one of the first group of internal clock signals generated by the first division circuit.

Clock generating circuit and semiconductor apparatus using the same

A signal generation circuit includes a first delay circuit, a second delay circuit, and a duty control circuit. The first delay circuit delays a first input signal to generate a first output signal. The second delay circuit delays a second input signal to generate a second output signal. The duty control circuit compares phases of the first and second output signals and changes the value of the second delay control signal, and then decreases the times, by which the first and second input signals are delayed, by the same value.

Signal generation circuit having minimum delay, semiconductor apparatus using the same, and signal generation method

A duty correction circuit comprises a first delay circuit, a second delay circuit, a bang-bang driver, a duty detection circuit, and a delay control circuit. The first delay circuit delays an input clock signal to generate a first delayed clock signal. The second delay circuit delays the input clock signal based on a delay control signal to generate a second delayed clock signal. The bang-bang driver generates first and second driving clock signals from the first and second delayed clock signals based on a locking signal and a duty detection signal. The duty detection circuit may detect duty cycles of the first and second driving clock signals and generate the duty detection signal. The delay control circuit may generate the delay control signal and the locking signal based on the duty detection signal.

Duty detection circuit, a duty correction circuit, and a semiconductor apparatus using the duty correction circuit

A phase detection circuit may include an edge trigger circuit, a strobe generation circuit and a phase detector. The edge trigger circuit generates a falling clock signal and a rising clock signal based on a reference clock signal and a target clock signal. The strobe generation circuit generates a falling strobe signal and a rising strobe signal having pulse widths varying based on a phase relationship between the reference clock signal and the target clock signal. The phase detector generates a phase detection signal based on the falling clock signal, the rising clock signal, the falling strobe signal and the rising strobe signal.

Phase detection circuit, clock generation circuit and semiconductor apparatus using the phase detection circuit

A clock generating circuit includes a first delay line, a second delay line, a selected phase mixing circuit and, a delay control circuit. The first delay line delays, based on a delay control signal, an input clock signal to generate a first delay clock signal. The second delay line delays, based on the delay control signal, the input clock signal to generate a second delay clock signal. The selected phase mixing circuit generates, based on a first selection signal and a second selection signal, an output clock signal from at least one between the first delay clock signal and the second delay clock signal. The delay control circuit monitors duty cycles of the first delay clock signal and the second delay clock signal to generate the first selection signal and the second selection signal thereby selecting at least one between the first delay line and the second delay line.

Clock generating circuit and a semiconductor system using the clock generating circuit

A phase mixing circuit includes a first driver comprising 2n inverters configured to drive a first clock signal, where n is a positive integer, and a first selection circuit configured to couple each of the 2n inverters of the first driver to a first mixing node, on the basis of a weight having first to 2nbits. The phase mixing circuit also includes a second driver comprising 2n inverters configured to drive a second clock signal and a second selection circuit configured to couple each of the 2n inverters of the second driver to the first mixing node, on the basis of an inverted signal of the weight.

Delay circuit and a delay locked loop circuit using the same

A clock generation circuit may include a clock receiver, a first delay loop circuit, and a second delay loop circuit. The clock receiver may receive a first clock signal and a second clock signal and generate a first reception clock signal and a second reception clock signal. The first delay loop circuit may receive the first reception clock signal and the second reception clock signal generate a reference clock signal. The first delay loop circuit may perform a delay-locking operation on the reference clock signal to generate a first delay locked clock signal. The second delay loop circuit may delay the first reception clock signal and the second reception clock signal based on the first delay locked clock signal and an internal clock signal to generate a first internal clock signal.

Clock generation circuit and semiconductor apparatus using the clock generation circuit

A signal generation circuit includes a synchronization circuit, a pulse width control circuit, and an output circuit. The synchronization circuit synchronizes an input signal with a clock signal to generate a synchronization signal. The pulse width control circuit generates a start signal from the synchronization signal and generate an end signal by delaying the synchronization signal by a time corresponding to an off control signal in synchronization with the clock signal. The output circuit generates an output signal based on the start signal and the end signal.

Signal generation circuit and a semiconductor apparatus using the signal generation circuit

A latched comparator includes a first amplification circuit, a second amplification circuit and a latch circuit. The first amplification circuit changes voltage levels of first and second output nodes based on first and second input signals when an operation speed of a semiconductor apparatus is relatively slow. The second amplification circuit changes voltage levels of third and fourth output nodes based on the first and second input signals when the operation speed of the semiconductor apparatus is relatively fast. The latch circuit generates first and second latch signals based on the voltage levels of the first and second output nodes or based on the voltage levels of the third and fourth output nodes according to the operation speed of the semiconductor apparatus.

Latched comparator, clock generation circuit and semiconductor apparatus relating to the latched comparator

A semiconductor device may include a first internal command generation circuit configured to advance a phase of a first external command in accordance with a delay time of an on die termination (ODT) path and a first latency and generate the first delay command; and a second internal command generation circuit configured to advance a phase of a second external command in accordance with a delay time of a clock path and a second latency and to generate a second delay command.

Semiconductor device

A semiconductor device may include a first internal command generation circuit, a first DLL circuit, a second internal command generation circuit, and a second DLL circuit. The first internal command generation circuit may generate a first delay command in response to a first external command, a first latency, a first clock, a first delay control signal, and a second clock. The first DLL circuit may generate the first delay control signal and the first second clock in response to the first clock. The second internal command to generation circuit may generate a second delay command in response to a second external command, a second latency, the first clock, a second delay control signal, and a third clock. The second DLL circuit may generate the second delay control signal and the third clock in response to the first clock.

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Icheon-si, South Korea

Gyu Tae Park