Hyundai Electronics Industries Co. Ltd.

Hynix Semiconductor Inc.

Skhynix Inc.

Gyu Seog Cho

Jong Wook Lee

Tae Jin Kim

Kyung Seok Oh

Soo Won Lee

Seung Hwan Baik

Yong Taik Kim

Kyung Wook Park

A semiconductor memory device and a method of operating the same perform a program loop, including a program operation and a program verification operation based on a sub-verification voltage smaller than a target verification voltage and the target verification voltage, to the memory cells until a threshold voltage of the memory cells is greater than the target verification voltage. A positive voltage, supplied to the bit line of the memory cell of which the threshold voltage is higher than the sub-verification voltage, is increased whenever the program operation is performed, and thus a threshold voltage distribution of the memory cells may be improved.

Semiconductor memory device and method of operating the same

A semiconductor device and a method for manufacturing the same are disclosed. The disclosed semiconductor device includes a semiconductor substrate having a device isolation structure for delimiting an active region, the active region being recessed and grooves being defined in channel forming areas of the active region; gates formed in and over the grooves; gate spacers formed on both sidewalls of the gates over portions of the recessed active region which are positioned on both sides of the gates; an LDD region formed in the active region under the gate spacers; junction areas formed in the active region on both sides of the gates including the gate spacers; and landing plugs formed on the junction areas.

Manufacturing method of transistor structure having a recessed channel

Semiconductor device with recessed active region and gate in a groove

The recess channel transistor includes: a semiconductor substrate including a device insulation layer defining an activation region in which recesses are formed; insulation buffer patterns, each of which is formed at an opening of the recess on a surface of the substrate; gates, each of which includes a recess gate formed in the recess and a top gate formed on the substrate; spacers, each of which is formed at both sides of the gate; and a source region and a drain region formed at both sides of each gate on the surface of the substrate, where the source and drain regions have an even doping profile due to the existence of insulation buffer patterns. Accordingly, characteristics of the transistor can be prevented from deteriorating due to misalignment of the top gate with the recess gate.

Recess channel transistor for preventing deterioration of device characteristics due to misalignment of gate layers and method of forming the same

There is disclosed a method of manufacturing a transistor in a semiconductor device. The present invention isolates a semiconductor substrate by an oxide layer with only a source, a drain and a channel region necessary for driving a transistor being left. Thus, it can obviate the current components due to parasitic factors to improve the punch-through characteristic.

Method of forming a transistor in a semiconductor device

A method for fabricating a semiconductor memory device using a silicon-on-insulator device, including forming a semiconductor memory device capable of reducing the topology between a cell region and a peripheral region and preventing floating body effect.

Semiconductor memory device and method for fabricating the same

A semiconductor memory device using a silicon-on-insulator device, including a semiconductor memory device capable of reducing the topology between a cell region and a peripheral region and preventing floating body effect.

Disclosed is a method for fabricating CMOS device using a SOI substrate, and more particularly the method for fabricating CMOS device capable of improving mobility of electron and hole. The present invention provides a method for fabricating CMOS device comprising the steps of: providing an SOI substrate having a stacking structure of a base layer, a buried oxide layer and a semiconductor layer, wherein the SOI substrate is divided into a first region where a PMOS is formed later and a second region where an NMOS is formed later; forming first field oxide films to be contacted with the buried oxide layer by applying a thermal oxidation to a selected portion of the semiconductor layer being disposed in the first region of the SOI substrate; forming trenches with a depth to be contacted with the buried oxide layer in a selected portion of the semiconductor layer being disposed in the second region of the SOI substrate and then forming second field oxide films by filling the trenches with an insulating layer; and forming the PMOS in the portion of the semiconductor layer being defined by those first field oxide films, and the NMOS in the portion of the semiconductor layer being defined by those second field oxide films.

Method for fabricating CMOS device

The present invention relates to a method for fabricating a semiconductor laser diode in optical communication system, and the present invention uses both an oxide and a nitride pattern as an etch mask instead of the single oxide pattern in order to decrease the under cut of the edge of the oxide pattern.

Method for fabricating a laser diode

The present invention relates to a method for fabricating a semiconductor laser diode in optical communication system, having the steps for forming current blocking layers on the resulting structure of the mesa structure and then forming an opening through the current blocking layer on the mesa structure.

Growing community of inventors

Kyoungki-do, South Korea

Gyu Seog Cho