Samsung Electronics Co., Ltd.

Gyu-Chul Kim

Hoo-Sung Cho

Gi-Sung Yeo

Sung-Gon Jung

Man-Hyoung Ryoo

Chang-Min Park

Si-Hyeung Lee

Kang-Sik Cho

Sung-bong Kim

Yong In Park

Han-Soo Kim

Chul-Sung Park

Hoo-Seung Cho

According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed.

Semiconductor device having sufficient process margin and method of forming same

A memory device, such as a DRAM, SRAM or non-volatile memory device, includes a substrate, a gate electrode disposed on the substrate, and source and drain regions in the substrate adjacent respective first and second sidewalls of the gate electrode. First and second sidewall spacers are disposed on respective ones of the first and second sidewalls of the gate electrode. The first and second sidewall spacers have different dielectric constants. The first and second sidewall spacers may be substantially symmetrical and/or have substantially the same thickness.

Methods of fabricating memory devices with memory cell transistors having gate sidewall spacers with different dielectric properties

Memory devices with memory cell transistors having gate sidewell spacers with different dielectric properties

A semiconductor device includes an insulated gate electrode pattern formed on a well region. The semiconductor device further includes a sidewall spacer formed on sidewalls of the gate electrode pattern. A source region and a drain region are formed adjacent opposite sides of the gate pattern. In accordance with one embodiment of the present invention, one of the source or drain regions includes a first-concentration impurity region formed under the sidewall spacer. The semiconductor device further includes a silicide layer formed within the well region wherein at least a part of the silicide layer contacts a portion of the well region to bias the well region. A method of manufacturing the semiconductor device is also provided.

Semiconductor device having a merged region and method of fabrication

A semiconductor device and a fabrication method thereof are provided. The semiconductor device has a probing pad formed on a chip. The probing pad is connected to an output pad and an internal circuit though a fuse. After an electrical testing of the chip by the probing pad, the fuse is cut by a laser beam. Therefore, the probing pad is disconnected from the output pad and the internal circuit. The output pad is connected to an output lead of a package, which is encapsulating the chip. According to the device and the fabrication methods thereof, performance of the device can be enhanced by a low parasitic capacitance and a low parasitic resistance.

Semiconductor device having a fuse connected to a pad and fabrication method thereof

A semiconductor device includes a substrate of a first conductive type, and a well region of an opposite second conductive type is formed in the substrate. A first impurity region of the first conductive type extends to a first depth within the well region, and a second impurity region of the first conductive type is spaced from the first impurity region to define a channel region therebetween and extends to a second depth within the well region. Preferably, the second depth is greater than the first depth. A gate electrode is located over the channel region, and a silicide layer is formed at a third depth within the first impurity region. The third depth is less than the first depth, and a difference between the first depth and the third depth is less than or equal to a difference at which a leakage current from the silicide layer to the well region is sufficient to electrically bias the well region through the silicide layer.

Semiconductor device and method of fabricating a semiconductor device

A MOS transistor having a self-aligned well bias area and a method of fabricating the same provide for efficient application of well bias in a highly integrated semiconductor substrate without causing latch-up. The well bias area is formed at a trench, which is formed by etching a semiconductor substrate in a manner of self-alignment, so that well bias can be efficiently applied to the MOS transistor achieving reduction of the area of a chip without degradation of electrical characteristics.

MOS transistor having self-aligned well bias area

A disk drive mechanism includes a disk clamping apparatus which has an improved structure and which is easily fabricated, thereby to reduce costs. The disk clamping apparatus includes a clamp having a plurality of clamp jaws movable horizontally, such that the apparatus is compact. The clamp also includes first and second grooves formed according to central hole sizes of the disks to be accommodated on the turntable so that the clamp can be used for both a compact disk and a laser disk.

Growing community of inventors

Gyeonggi-do, South Korea

Gyu-Chul Kim