Samsung Electronics Co., Ltd.

Gyosoo Choo

Daeseok Byeon

Kiwhan Song

Youngwoo Park

Seunghoon Lee

Dongku Kang

Ji-sang Lee

Moosung Kim

Sukkang Sung

YongSung Cho

Inho Kang

Sungwhan Seo

Beakhyung Cho

Pil Seon Yoo

Min-Hwi Kim

Jinwoo Choi

Tae-Hong Kwon

Cheongwon Lee

The present disclosure provides serial-gate transistors and nonvolatile memory devices including serial-gate transistors. In some embodiments, a nonvolatile memory device includes a plurality of memory blocks, a plurality of pass transistor blocks, and a plurality of gates sequentially arranged in a horizontal direction in a gate region above a semiconductor substrate. Each of the plurality of pass transistor blocks includes a plurality of serial-gate transistors configured to transfer a plurality of driving signals to a corresponding memory block of the plurality of memory blocks. Each of the plurality of serial-gate transistors includes a first source-drain region, a gate region, and a second source-drain region that are sequentially arranged in a horizontal direction at a semiconductor substrate. The plurality of gates are electrically decoupled from each other. A plurality of block selection signals respectively applied to the plurality of gates are controlled independently of each other.

Serial-gate transistor and nonvolatile memory device including the same

Provided is a non-volatile memory device including a page buffer circuit having a multi-stage structure, wherein a stage of the multi-stage structure includes a high voltage region, a first low voltage region, and a second low voltage region. The high voltage region includes a first high voltage transistor connected to one of first to sixth bit lines and a second high voltage transistor connected to one of seventh to twelfth bit lines, the first low voltage region includes a first transistor connected to the first high voltage transistor, and the second low voltage region includes a second transistor connected to the second high voltage transistor. Each of the first low voltage region and the second low voltage regions has a first width corresponding to a pitch of six bit lines, and the high voltage region has a second width corresponding to a pitch of twelve bit lines.

Non-volatile memory device with high voltage region and low voltage region

Memory devices having an asymmetric page buffer array architecture are provided. The memory device includes a memory cell array in which each of plural memory planes is included in a cell array structure, and a row decoder array and a page buffer array included in a peripheral circuit structure vertically overlap the cell array structure. The row decoder array is buried in a region vertically overlapping a word line step region of the cell array structure and a partial region of a memory cell array adjacent to the word line step region. In the page buffer array, bit lines of a partial region of the memory cell array in which the row decoder array is buried are connected to a first page buffer array, and bit lines not included in the partial region are connected to a second page buffer array.

Memory device having asymmetric page buffer array architecture

An embodiment provides a test element group (TEG) circuit, including: a first pad configured for a test voltage to be applied; an amplifier including a first input terminal connected to the first pad, a second input terminal connected to a first terminal of a test transistor, and an output terminal electrically connected to the second input terminal; a variable resistor including one terminal connected to the output terminal of the amplifier and the other terminal connected to the first terminal of the test transistor; and a gate driving circuit that supplies a gate voltage to a gate of the test transistor.

TEG circuit, semiconductor device, and test method of the TEG circuit

Various example embodiments provide a flash memory device, comprising a cell string; a page buffer connected to the cell string and a bit line and configured to sense data stored in a selected memory cell by precharging a sensing node connected to the bit line; and a voltage regulator. The page buffer comprises a latch including first and second inverters coupled between a latch node and an inverted latch node; and a pull-down NMOS transistor for tripping the sensing result of the selected memory cell to the latch node. The voltage regulator adjusts a trip voltage by providing the source voltage to the pull-down NMOS transistor. The flash memory device reduce a trip voltage variation range by using only the pull-down NMOS transistor characteristics. Also, an OFF cell margin and an ON cell margin may be secured by adjusting the level of the trip voltage using the source voltage.

Flash memory device for adjusting trip voltage using voltage regulator and sensing method thereof

A nonvolatile memory device includes a memory cell, a bit line, a page buffer, and a control logic. The page buffer is connected to the memory cell through the bit line and the page buffer is configured to precharge the bit line to perform a desired operation. The desired operation may be one of a read operation and a verify operation. The control logic is configured to control bit line development time differently according to a temperature after precharging the bit line during the desired operation. The control logic is configured to determine the bit line development time according to a period of a reference clock signal that includes a different frequency depending on the temperature and/or a temperature compensation pulse signal including a pulse width that varies based on the temperature.

Nonvolatile memory device and method of operating the same

A nonvolatile memory device includes a substrate, a plurality of memory cells stacked in a direction perpendicular to the substrate, word lines connected to the memory cells, a ground select transistor between the memory cells and the substrate, a ground select transistor between the memory cells and the substrate, a ground select line connected to the ground select transistor, a bit line on the memory cells, and a string select transistor between the memory cells and the bit line. In an erase operation, the ground select line is floated at a time when a specific time passes after the erase voltage is provided to the substrate. And the ground select line is floated at different times depending on a temperature.

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Yongin-si, South Korea

Gyosoo Choo