Etron Technology, Inc.

Piecemakers Technology, Inc.

Other

Piecemakers Technology, Incorporation

Gyh-Bin Wang

Tah-Kang Joseph Ting

Ming-Hung Wang

Li-Chin Tien

Der-Min Yuan

Chun Shiah

Chien-Te Wu

Hsien-Sheng Huang

Yung-Ching Hsieh

Chun-Peng Wu

Ming-Song Huang

Wen-Ming Lu

Cheng-En Shieh

Yin-Shing Lieu

Chun-Kai Wang

Ming-Song Hwang

Chih-Tung Wang

Page data can be propagated sequentially from a section to the neighboring section, and from this section to subsequent section adjacent to it until a page register set is reached. In a described apparatus based on this page-data-copy scheme, access data from a page register (which is also used for storing the data accessed using the page-data-copy scheme) with a conditional read-access method in conjunction with an arithmetic unit can execute the arithmetic process of an AI system.

Apparatus for data processing in conjunction with memory array access

Voltages loaded onto the bit lines in a first CA section of a memory array can be latched by enabling the BLSA between the first section and a second section adjacent to the first section causing latched voltages to propagate to bit lines in the second section. Voltages propagated to the bit lines in the second section using the latches between the second section and a third section. Voltages can be propagated sequentially from section to subsequent adjacent section until a target location is reached. The scheme can be applied as a method of page-data write access in a memory chip, of which page data can be propagated sequentially from section to subsequent adjacent section until a target location is reached, and then, activating a word line in a section of the memory comprising the target location to write voltages to the memory cells at the target location.

DRAM with inter-section, page-data-copy scheme for low power and wide data access

An apparatus for enhancing prefetch access in a memory module may include a memory chip. The memory chip includes a memory cell array, a plurality of bit lines and a plurality of word lines, a plurality of BLSAs, and a plurality of main data lines. The memory cell array may be arranged to store data, and the plurality of bit lines and the plurality of word lines may be arranged to perform access control of the memory cell array. The plurality of BLSAs may sense a plurality of bit-line signals restored from the plurality of memory cells and convert the plurality of bit-line signals into a plurality of amplified signals, respectively. The main data lines may directly output the amplified signals, through selection of CSLs of the BLSAs on the memory chip, to a secondary semiconductor chip, for performing further processing of the memory module, thereby enhancing the prefetch access.

Apparatus for enhancing prefetch access in memory module

A semiconductor chip set with double-sided off-chip bonding structure in the disclosure comprises at least one first off-chip bonding structure formed above a first surface of the semiconductor chip set, and at least one second off-chip bonding structure formed above a second surface of the semiconductor chip set, wherein the first surface is opposite to the second surface and each of the first off-chip bonding structure and the second off-chip bonding structure is used for connecting to an electrical connecting point external to the semiconductor chip set through bonding wire, through-silicon via (TSV) or micro bump.

Semiconductor chip set with double-sided off-chip bonding structure

A memory chip architecture includes a plurality of test pads, a plurality of interface pads, a function block and an embedded test block. The function block is coupled to the interface pads. The embedded test block is coupled to the test pads. The embedded test block is connected to an access port physical layer (PHY) through the interface pads. The interface pads are disposed between the function block and the embedded test block. The embedded test block is arranged for generating at least one test pattern as a test signal, and outputting the test signal to the function block through the interface pads to test the function block.

Circuit topology of memory chips with embedded function test pattern generation module connected to normal access port physical layer

A memory architecture includes K first control lines, M groups of second control lines and a memory cell array. K and M are positive integers. Each group of second control lines includes at least one second control line. The memory cell array includes M memory banks. Each memory bank is coupled to the K first control lines. The M memory banks are selected according to M bank select signals respectively so as to receive a shared set of first control signals through the K first control lines. The M memory banks are coupled to the M groups of second control lines respectively, and receive independent M sets of second control signals through the M groups of second control lines respectively. Each memory bank performs one of a column select operation and a sense amplification operation according to the set of first control signals and a set of second control signals.

Memory architecture with multi-bank memory cell array accessed by local drive circuit within memory bank

A control method of a memory device, a memory device and a memory system are provided. The memory system includes a memory control unit and a memory die. The memory die performs a data access operation asynchronously with respect to a system clock according to address information and an access signal generated from the memory control unit. When operating in a read mode, the memory die generates a data tracking signal according to a memory internal read time which is an elapsed time for data to be read to be read out from the memory die. The memory control unit and the memory die obtain required data according to respective data tracking signals transmitted therebetween. The control method defines an asynchronous memory interface protocol which realizes reliable and high speed data transmission.

Method for controlling memory device asynchronously with respect to system clock, and related memory device and memory system

A memory device includes a common data bus, a plurality of memory banks and a control circuit. The memory banks are coupled to the common data bus. The memory banks share the common data bus. Each of the memory banks includes a storage device and a data register. The data register is coupled between the storage device the common data bus, and is arranged for storing data read from the storage device. The control circuit is coupled to storage devices and data registers of the memory banks, and is arranged for referring to an address signal and an access signal to control the storage device of said each memory bank to output the data to the corresponding data register, and referring to the address signal and a programmable latency time to control the data registers to output data from the memory banks to the common data bus.

Multi-bank memory device and system

A memory architecture includes K first wordlines, M groups of second wordlines, a memory cell array and M switch circuits. K and M are positive integers. Each group of second wordlines includes a plurality of second wordlines. The memory cell array includes M memory banks. The M memory banks are coupled to the M groups of second wordlines respectively, and receive independent M sets of second wordline signals through the M groups of second wordlines respectively. M switch circuits are disposed in correspondence with the M memory banks respectively. Each switch circuit selectively couples the K first wordlines to a corresponding memory bank so that the corresponding memory bank receives a shared set of first wordline signals through the K first wordline. Each memory bank performs a data access operation according to the received set of first wordline signals and a corresponding set of second wordline signals.

Memory architecture dividing memory cell array into independent memory banks

A high speed test circuit receives a tester clock from a tester and it conducts a test on a circuit under test. The high speed test circuit generates a high frequency clock according to the tester clock, so it is capable of operating in two frequencies. The high speed test circuit tests the circuit under test according to the high frequency clock, and it performs a low speed operation according to a low frequency clock, which is for example the tester clock.

High speed test circuit and method

A method and an apparatus are provided for image stabilization for the output of analog-to-digital converters (ADC) and for phase-locked loops (PLL). The digital coding at the output of ADCs and PLLs is filtered by this method and apparatus to eliminate the noise which has contaminated the coding. The noise sources are noise picked up by the cable, system board noise, ADC power and ground noise paths, and switching noise. The differences of energy level of sequential pixels in the ADC and PLL digital outputs used in image displays are used to decide if correction is required. The method of image noise filtering is compatible with programmable circuitry. This allows the method to be tuned for optimal image stabilization.

Digitized image stabilization using energy analysis method

The method and circuit provide an effective implementation to handle the data transferring problem between multiple clock domains. A shift circuit shifts the incoming data stream, which comprises N parallel signals divided into a first group of parallel signals and a second group of parallel signals, to be in accordance with a first sequence of N sampling pulses, and a sampling module sequentially samples each signal in the first group signals and the second group signals with the N sampling pulses in a second sequence and outputs a serial signal.

Method and circuit for transferring data stream across multiple clock domains

This invention provides a method and apparatus for displaying an unscaled image frame on an LCD panel. The method and apparatus uses the same line buffers available to the digital signal processor DSP formerly used for scaling the displayed image up or down in size. No extra frame buffers are required by this invention since the frame rates of the source image and the LCD panel are the same. The image frame buffer is written to the LCD panel on every other panel vertical synchronization pulse. The vertical synchronization timing is shifted to the left or right in the time domain to center the image on the LCD panel.

LCD controller which supports a no-scaling image without a frame buffer

A method to reduce clock noise in a multiple clock circuit is achieved. The method comprises, first, providing a periodic signal. Next, a first clock signal is provided having a frequency that is a constant multiple of the frequency of the periodic signal. Finally, a second clock signal is derived from the periodic signal. The second clock signal has a frequency that is a non-constant multiple of the periodic signal frequency. The non-constant multiple comprises the sum of a constant value plus a time-varying value. The spectral energy at the sum and difference frequencies of the first and second clock signals is reduced by frequency distribution spreading. A circuit is achieved comprising the above method.

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Hsinchu County, Taiwan

Gyh-Bin Wang