Samsung Electronics Co., Ltd.

Gyeong-Hee Kim

Jun-Eui Song

Soo-cheol Lee

Byung-Kwan You

Hee-Jueng Lee

Provided is a method of forming a semiconductor device. A tunnel insulating layer is formed on a substrate having a cell region and a low voltage region. First and second charge storage gate patterns (e.g., floating gate patterns) are formed on the tunnel insulating layers of the cell and low voltage region, respectively. A blocking insulating layer and a control gate conductive layer are formed on the substrate in sequence. The control gate conductive layer, the blocking insulating layer, the second floating gate pattern and the tunnel insulating layer of the low voltage region are removed to expose the substrate of the low voltage region. The low-voltage gate insulating layer is formed on the exposed substrate. A low-voltage gate conductive pattern is formed on the low-voltage gate insulating layer.

Method of forming semiconductor device includeing forming control gate layer over each region and removing a portion of the tunnel insulating layer on the low voltage region

Semiconductor integrated circuit devices having SRAM cells and flash memory cells are provided. The devices include an integrated circuit substrate having an SRAM cell region, a flash memory cell region and a logic circuit region. An isolation layer is provided in a predetermined region of the substrate. The isolation layer defines a SRAM cell active region, a flash memory cell active region and a logic transistor active region in the SRAM cell region, the flash memory cell region and the logic circuit region, respectively. An SRAM cell gate pattern crosses over the SRAM cell active region. The SRAM cell gate pattern includes a main gate electrode and a dummy gate electrode which are sequentially stacked. A flash memory cell gate pattern crosses over the flash memory cell active region. The flash memory cell gate pattern includes a control gate electrode crossing over the flash memory cell active region as well as a floating gate interposed between the control gate electrode and the flash memory cell active region. A logic gate pattern crosses over the logic transistor active region. The logic gate pattern also includes a main gate electrode and a dummy gate electrode which are sequentially stacked. Related methods of fabricating semiconductor integrated circuit devices are also provided.

Methods of fabricating semiconductor integrated circuit devices including SRAM cells and flash memory cells

A semiconductor memory device is provided for preventing loss of cell data and reduction of a standby current. The semiconductor memory device includes a first conductivity type semiconductor substrate connected to a ground voltage, a first well region of second conductivity type formed over the semiconductor substrate and connected to the ground voltage, a second well region of the first conductivity type embedded in the first well region, a first impurity region of the second conductivity type embedded in the second well region and connected to an input/output pad, and one or more additional impurity regions embedded in the second well region separately from the first impurity region, the one or more additional impurity regions being connected to the ground voltage.

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Gyeonggi-do, South Korea

Gyeong-Hee Kim