Tokyo Electron Limited

Gyanaranjan Pattanaik

Gerrit J Leusink

Cory Wajda

Kai-Hung Yu

Robert Daniel Clark

Kandabara N Tapily

Hiroaki Niimi

David L O'Meara

Nicholas Joy

Takahiro Hakamata

Eric Chih-Fang Liu

Yun Han

Shihsheng Chang

Henan Zhang

Ying Trickett

Hisashi Higuchi

Robert Clark

Embodiments of methods are provided for thermal dry etching of a ruthenium (Ru) metal layer. In the disclosed embodiments, a substrate containing a Ru metal layer formed thereon is exposed to a gas pulse sequence, while the substrate is held at a relatively high substrate temperature (e.g., a temperature greater than or equal to about 160° C.), to provide thermal etching of the Ru metal layer. As described further herein, the gas pulse sequence may generally include a plurality of gas pulses, which are supplied to the substrate sequentially with substantially no overlap between gas pulses. The gas pulses supplied to the substrate form: (i) volatile reaction products that are vaporized from the Ru surface, and (ii) non-volatile oxide surface layers that are removed from the Ru surface by the next gas pulse, resulting in atomic layer etching (ALE) of the Ru metal layer.

Thermal etching of ruthenium

A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, forming a nucleation enhancement layer on a sidewall of the first layer in the recessed feature and depositing a metal layer in the recessed feature by vapor phase deposition, where the metal layer is deposited on the second layer and on the nucleation enhancement layer. An initial metal layer may be selectively formed on the second layer in the recessed feature before forming the nucleation enhancement layer.

Method for filling recessed features in semiconductor devices with a low-resistivity metal

A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, and pre-treating the substrate with a surface modifier that increases metal deposition selectivity on the second layer relative to on the first layer, depositing a metal layer on the substrate by vapor phase deposition, where the metal layer is preferentially deposited on the second layer in the recessed feature, and removing metal nuclei deposited on the first layer, including on a field area and on sidewalls of the first layer in the recessed feature, to selectively form the metal layer on the second layer in the recessed feature. The steps of pre-treating, depositing and removing may be repeated at least once to increase a thickness of the metal layer in the recessed feature.

A semiconductor device and a method of forming a semiconductor device. The semiconductor device includes a first raised feature in a n-type channel field effect transistor (NFET) region on a substrate, a first doped epitaxial semiconductor material grown on the first raised feature, a first metal contact on the first doped epitaxial semiconductor material, a first metal nitride on the first metal contact, and a first ruthenium (Ru) metal plug on the first metal nitride. The device further includes a second raised feature in a p-type channel field effect transistor (PFET) region on the substrate, a second doped epitaxial semiconductor material grown on the second raised feature, a second metal contact on the second doped epitaxial semiconductor material, a second metal nitride on the second metal contact, and a second ruthenium (Ru) metal plug on the second metal nitride.

Dual metal contacts with ruthenium metal plugs for semiconductor devices

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Albany, NY, United States of America

Gyanaranjan Pattanaik