Spansion Llc.

Gwyn Robert Jones

Mark W Randolph

Edward Franklin Runnion

Yi He

Zhizheng Liu

Xuguang Alan Wang

Gulzar Ahmed Kathawala

Ming-Sang Kwan

Sheung-Hee Park

Sung-Chul Lee

Sean Michael O'Mullan

Wing Leung

John Anthony Darilek

Adam Shackleton

Jacob Marcantel

Rick Anundson

Xiaojian Chu

Abhijit Raghunathan

Asif Arfi

Providing for suppression of room temperature electronic drift in a flash memory cell is provided herein. For example, a soft program pulse can be applied to the flash memory cell immediately after an erase pulse. The soft program pulse can help to mitigate dipole effects caused by non-combined electrons and holes in the memory cell. Specifically, by utilizing a relatively low gate voltage, the soft program pulse can inject electrons into the flash memory cell proximate a distribution of uncombined holes associated with the erase pulse in order to facilitate rapid combination of such particles. Rapid combination in this manner reduces dipole effects caused by non-combined distributions of opposing charge within the memory cell, reducing room temperature program state drift.

Room temperature drift suppression via soft program after erase

Methods and systems for accurately programming or erasing one or more memory cells on a selected wordline of a memory device are provided. In one embodiment, the memory device comprises a memory array, a threshold voltage measuring component configured to measure a threshold voltage of each memory cell on the selected wordline of the memory array, and an average threshold voltage determining component configured to determine an average threshold voltage result uniquely associated with the selected wordline, based on the measured threshold voltages. The memory device is configured to program one or more of the memory cells to a predefined program level relative to the determined average threshold voltage, or to erase memory cells of the selected wordline to the determined average threshold voltage. The method is particularly useful for multi-level flash memory cells to reduce charge loss while improving data reliability and Vt distributions of the programmed element states.

Algorithm for charge loss reduction and Vt distribution improvement

A method of erasing a block of flash memory cells by applying a ramped gate erase voltage to the block of memory cells. When an erase verify of the block of memory cells indicates that erasure has not been successfully completed another erase voltage with a greater absolute value than the initial erase voltage can be applied to the block of memory cells until erasure is complete.

Ramp gate erase for dual bit flash memory

A method is provided for erasing a memory device including a number of memory cells, the memory cells including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes erasing a group of memory cells to lower a maximum threshold voltage of the group of memory cells below a first predetermined level. The group of memory cells is soft-programmed to raise a minimum threshold voltage of the group of memory cells above a second predetermined level. The group of memory cells is erased, following soft-programming, resulting in a reduced threshold voltage distribution associated with the group of memory cells.

Methods and systems for reducing the threshold voltage distribution following a memory cell erase

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Sunnyvale, CA, United States of America

Gwyn Robert Jones