Marvellworld Trade Ltd.

Marvell International Limited

Synaptics Corporation

Gwyn Edwards

Nikhil Balram

Sanjay Saran Garg

Richard David Taylor

Vipin Namboodiri

Shilpi Sahu

Bipasha Ghosh

Loren Tomasi

Kaip Sridhar

Systems and methods are provided for improving the visual quality of low-resolution video displayed on large-screen displays. A video format converter may be used to process a low-resolution video signal from a media providing device before the video is displayed. The video format converter may detect the true resolution of the video and deinterlace the video signal accordingly. For low-resolution videos that are also low in quality, the video format converter may reduce compression artifacts and apply techniques to enhance the appearance of the video.

Methods and systems for improving low-resolution video

The invention includes a system and the associated method for decoding multiple video signals. The video signals may be component video, composite video or s-video signals each having multiple portions using a multimode video decoder. A selection stage may combine the multiple video signals and select some of their video signal portions for processing. The selection stage may time-multiplex some of the video signal portions. An analog to digital conversion stage may be shared by the time-multiplexing of the video signals. A decoder stage may decode the various signal portions and provide decoded output video signals. These feature may reduce the overall cost of the system. Various clock signals may be used to operate various stages of a multimode video decoder. Some of the clock signals may run at different frequencies and others may operate at a different phase.

Shared memory multi video channel display apparatus and methods

A shared memory video processor including signal processing circuitry. The signal processing circuitry may enable a noise reducer and a de-interlacer to share access to field buffers in a memory device to store various field lines. Some of the stored field lines may also be shared within the signal processing circuitry. The sharing of some stored field lines reduces overall memory bandwidth and capacity requirements. The signal processing circuitry may be capable of performing multiple field line processing. A set of field line buffers may be provided to store field lines for multiple field segments and may provide the data to the corresponding inputs of the signal processing circuitry. To further reduce storage, some of the field line buffers may also be shared among the signal processing circuitry.

A scaler positioning module may receive a video signal selected from among a plurality of video signals. The scaler positioning module may include scaler slots for arranging the signal path of the selected video signal through at least one scaler in the scaler positioning module. The scaler slots may enable the scaler positioning module to operate in three modes. The three modes may enable the scaler positioning module to output scaled data without memory operations, scale prior to a memory write, and scale after a memory read. A blank time optimizer (BTO) may receive data from the scaler positioning module at a first clock rate and distributed memory accesses based on a bandwidth requirement determination. The BTO may access memory at a second clock rate. The second clock rate may be slower than the first which may reduce memory bandwidth and enable another video signal to access memory faster.

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Mountain View, CA, United States of America

Gwyn Edwards