Skhynix Inc.

Gwi Han Ko

Hyung Jin Choi

Chan Hui Jeong

Sung Hun Kim

Jae Hyeon Shin

Hyun Soo Lee

Se Chun Park

Gwan Park

Provided herein may be a memory device for performing a program operation including program loops and a method of operating the same. The method of operating a memory device may include performing a first program loop of increasing threshold voltages of first memory cells selected by a first drain select line among a plurality of memory cells coupled to a word line, performing a second program loop of increasing threshold voltages of second memory cells selected by a second drain select line among the plurality of memory cells, and alternately repeating the first program loop and the second program loop such that respective threshold voltages of the first memory cells and the second memory cells are increased to respective threshold voltages corresponding to respective target program states.

Memory device for performing program operation including program loops and method of operating the same

A memory device includes: a plurality of memory cells; a peripheral circuit configured to perform a plurality of program loops each including a program voltage apply operation of applying a program voltage to selected memory cells, and a verify operation of verifying a program state of the selected memory cells; and a control logic configured to control the peripheral circuit to apply program voltages increasing in a step-wise manner by a first step voltage in program loops in a first state, and increasing by a second step voltage that is lower than the first step voltage in program loops in a second state that occur after the program loops in the first state. The first state and the second state of the program loops are determined based on when a verify operation on a program state having a highest threshold voltage is performed.

Memory device for performing program operation according to incremental step pulse programming method, storage device including the same, and operating method of the memory device

The present technology may include a voltage generation circuit configured to generate a plurality of voltages in response to at least one voltage control signal, and control logic configured to generate the at least one voltage control signal in order to adjust at least one of an under drive time and an under drive offset during an under drive operation of a semiconductor apparatus according to a temperature information signal and a pre-stored temperature characteristic signal of the semiconductor apparatus.

Under drive control circuit and semiconductor apparatus including the under drive control circuit

A semiconductor apparatus includes a memory cell array and a control circuit. The control circuit is configured to perform a program operation on target cells within the memory cell array, the program operation including a plurality of loops. The control circuit may be configured to apply a bit line voltage having a predetermined level to bit lines in loops in which a pass voltage having a first level is applied among the plurality of loops, and configured to apply the bit line voltage having a higher level than the predetermined level to the bit lines in loops in which the pass voltage having a second level higher than the first level is applied among the plurality of loops.

Semiconductor apparatus with program operation control

A memory device may include a first sub-block and a second sub-block each including a plurality of select transistors and a plurality of memory cells, a peripheral circuit performing a read operation on data stored in the first sub-block, and a control logic controlling the peripheral circuit to turn on the plurality of select transistors included in each of the first and second sub-blocks and apply a read voltage to a selected word line among a plurality of word lines.

Memory device and operating method thereof

A memory device and method of operating the same. A memory device includes a memory block, a peripheral circuit, and a program operation controller. The memory block includes a first sub block connected to a first drain select line and a first source select line, and a second sub block connected to a second drain select line and a second source select line, and each of the first sub block and the second sub block is connected to a plurality of word lines and a common source line. The program operation controller controls the peripheral circuit to transfer a precharge voltage to the channel region through the common source line or a plurality of bit lines connected the memory block, and to apply a control voltage to the first and second source select lines at different time points or to apply the control voltage to the first and second drain select lines at different time points in the step of precharging the channel region.

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Gyeonggi-do, South Korea

Gwi Han Ko