Advanced Micro Devices Corporation

Gwangwoo Johnny Choe

James R MacDonald

Jim MacDonald

A fully pipelined parallel multiplier with a fast clock cycle. The pipelined parallel multiplier contains three units: a bit-product matrix unit, a reduction unit, and an addition unit. The bit-product matrix is configured to receive two binary numbers, a multiplier and a multiplicand. A bit-product matrix is formed based on these two numbers. The bit-product matrix unit forms a first pipeline stage. The bit-product matrix is latched to the reduction unit using d-type latch circuits. The reduction unit includes a plurality of reduction stages, with each reduction stage acting as a pipeline stage. The reduction unit reduces the matrix down to a two-row matrix. Intermediate results are latched from one stage to the next using d-type latch circuits. The reduction unit also contains a plurality of half-adder and full-adder circuits. The final two-row matrix formed by the reduction unit is then latched to an addition unit. The addition unit includes one or more stages of addition, with each stage also acting as a pipeline stage. Carry lookahead adder (CLA) circuits are cascaded to perform the addition, with one CLA per addition stage. Results from each addition stage are latched to the next stage using d-type latch circuits. The output from the final stage is the final product of the multiplication.

Fully pipelined parallel multiplier with a fast clock cycle

A system and method for computing the cosine of an input value. The system comprises a logical processing unit and an addition unit. The logical processing unit comprises an input bus with a plurality of input lines for receiving an input angle value. The logical processing unit includes a first plurality of gates, preferably AND gates, coupled to the input bus. Each gate of the first plurality of gates couples to two or more of the input lines. The logical processing unit generates N output operands on N corresponding output buses. At least one of the output buses includes (a) at least one output line coupled to an output of one of the first plurality of gates, and (b) at least one output line coupled to one of the input lines of the input bus. The number N of output buses is greater than or equal to two. The addition unit couples to the N output buses of the logical processing unit, and is configured to perform an addition of the N binary operands provided on the N output buses. The addition unit generates a resultant number which represents the cosine of the input operand conveyed on the input bus. The input angle value is assumed to have a predetermined number of leading zeros. In general, output lines are coupled to (a) input lines, (b) outputs of gates, or (c) set equal to zero.

Cosine algorithm for relatively small angles

A system and method for evaluating one or more functions using a succession of CORDIC stages/iterations followed by a residual rotation. The succession of CORDIC stages are preferably partitioned into (a) a Z path which operates on an input angle and generates an output angle, and (b) an X/Y path which operates on an input point and generates an output point. The residual rotation rotates the output point by the output angle to generate a resultant point using a small angle approximation for sine and an accurate evaluation for sine of the output angle. The number of CORDIC stages in the succession is chosen so that the error in the coordinates of the resultant point induced by the approximation of sine is smaller than a desired amount. In particular, the number of CORDIC stages in the succession is chosen to be greater than or equal to (N&plus;1)/3 in order to guarantee N bits of precision in coordinates of the resultant point. The Z path has a propagation time which is smaller than the X/Y path. This allows the cosine computation unit to generate the cosine of the output angle prior to the time when the X/Y path generates the output point. Thus, the residual rotation may be performed immediately upon generation of the output point.

Fast CORDIC algorithm with sine governed termination

A plurality of data devices are interfaced to a microprocessor using a serial data transfer mechanism. The parallel data from the data devices is serialized. The serial data streams are multiplexed via a data multiplexer. An index signal identifies the data device from which the serial data is received/transmit. When a receive buffer is at a predefined level of emptiness, a bit associated with that buffer is asserted. Likewise, when a transmit buffer is at a predefined level of emptiness, a bit within the index register associated with the transmit buffer is asserted. The assertion of a bit within the index register generates an interrupt. A CPU core receives the interrupt signal and reads the index register to determine which buffers need servicing. The CPU core deasserts one bit of the index register, which indicates the CPU core is going to service the buffer associated with that bit. If the bit in the index register is associated with a receive buffer, the deassertion of the bit causes the receive buffer to output receive data to the CPU core. Likewise, if the bit deasserted by the CPU core is associated with the transmit buffer, the deassertion of the bit within the index register causes the transmit buffer to input data from the CPU core.

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Austin, TX, United States of America

Gwangwoo Johnny Choe