Samsung Electronics Co., Ltd.

Gwang-Hyun Baek

Jongchul Park

Jong-Kyu Kim

Jung-Ik Oh

Jaehun Seo

Inho Kim

Sangmin Lee

Sechung Oh

Sang-Kuk Kim

Vladimir Urazaev

Hyungjoon Kwon

Ken Tokashiki

Hyun-woo Yang

Jong-Chul Park

Ilmok Park

Hyung-joon Kwon

Seulji Song

Ki-Jeong Kim

Ho-Ki Lee

Chang-Woo Sun

Kyungrae Byun

O Ik Kwon

Yun Seung Kang

Du-Chul Oh

Jin-Kwan Lee

Hye Ji Yoon

Tae Hyung Lee

Su Jin Jeon

A semiconductor memory device in which performance is improved by reducing a wiring resistance is provided. The semiconductor memory device comprising an inter-wiring insulation film on a substrate, a first wiring pattern extending in a first direction, in the inter-wiring insulation film, a barrier insulation film that is on an upper surface of the inter-wiring insulation film, a barrier conductive pattern electrically connected to the first wiring pattern, in the barrier insulation film, a memory cell electrically connected to the barrier conductive pattern and including a selection pattern and a variable resistor pattern, and a second wiring pattern extending in a second direction intersecting the first direction, on the memory cell, wherein a width of the barrier conductive pattern in the second direction is different from a width in the second direction of a portion of the memory cell that is adjacent to the barrier conductive pattern.

Semiconductor memory devices and methods for fabricating the same

A variable resistance memory device includes a substrate. A first conductive line is disposed on the substrate and extends primarily in a first direction. A second conductive line is disposed on the substrate and extends primarily in a second direction. The second direction intersects the first direction. A phase change pattern is disposed between the first conductive line and the second conductive line. A bottom electrode is disposed between the phase change pattern and the first bottom electrode includes first a first sidewall segment that connects the first conductive line and the phase change pattern to each other. The phase change pattern has a width in the first direction that decreases toward the substrate. The first sidewall segment has a first lateral surface and a second lateral surface that face each other. A lowermost portion of the phase change pattern is disposed between the first lateral surface and the second lateral surface.

Variable resistance memory device and method of fabricating the same

Provided herein are methods of fabricating a magnetic memory device including forming magnetic tunnel junction patterns on a substrate, forming an interlayered insulating layer on the substrate to cover the magnetic tunnel junction patterns, forming a conductive layer on the interlayered insulating layer, patterning the conductive layer to form interconnection patterns electrically connected to the magnetic tunnel junction patterns, and performing a cleaning process on the interconnection patterns. The cleaning process is performed using a gas mixture of a first gas and a second gas. The first gas contains a hydrogen element (H), and the second gas contains a source gas different from that of the first gas.

Methods of forming an interconnection line and methods of fabricating a magnetic memory device using the same

A semiconductor device includes a magnetic tunnel junction structure on a lower electrode, an intermediate electrode on the magnetic tunnel junction structure, and an upper electrode on the intermediate electrode, wherein the intermediate electrode includes a lower portion and an upper portion having a side surface profile different from that of the lower portion.

Semiconductor device having magnetic tunnel junction structure and method of forming the same

Provided are semiconductor devices and methods of fabricating the same. The semiconductor device may include lower wires, upper wires crossing the lower wires, select elements provided at intersections between the lower and upper wires, and memory elements provided between the select elements and the upper wires. Each of the memory elements may include a lower electrode having a top width greater than a bottom width, and a data storage layer including a plurality of magnetic layers stacked on a top surface of the lower electrode and having a rounded edge.

Semiconductor devices and methods of fabricating the same

A method for forming a pattern, the method including forming an etch target layer on a substrate; patterning the etch target layer to form patterns; and performing a pre-oxidation trim process a plurality of times, the pre-oxidation trim process including performing an oxidation process to form an insulating layer on a sidewall of each of the patterns; and performing a sputter etch process to remove at least a portion of the insulating layer.

Method for forming patterns and method for manufacturing magnetic memory device using the same

A memory device including a substrate, an insulating layer on the substrate, the insulating layer including a first region having a first top surface and a second region having a second top surface, the second top surface being lower than the first top surface with respect to the substrate, the first region including a first through hole penetrating therethrough, the second region including a second through hole penetrating therethrough, a first conductive pattern filling the first through hole, a second conductive pattern at least partially filling the second through hole, a magnetic tunnel junction pattern on the first conductive pattern, and a contact plug coupled to the second conductive pattern may be provided. Further, a method of fabricating the memory device also may be provided.

Memory device and method of fabricating the same

In a method of an MRAM device, first and second patterns are formed on a substrate alternately and repeatedly in a second direction. Each first pattern and each second pattern extend in a first direction perpendicular to the second direction. Some of the second patterns are removed to form first openings extending in the first direction. Source lines filling the first openings are formed. A mask is formed on the first and second patterns and the source lines. The mask includes second openings in the first direction, each of which extends in the second direction. Portions of the second patterns exposed by the second openings are removed to form third openings. Third patterns filling the third openings are formed. The second patterns surrounded by the first and third patterns are removed to form fourth openings. Contact plugs filling the fourth openings are formed.

Methods of manufacturing magnetoresistive random access memory devices

A semiconductor memory device includes conductive patterns vertically stacked on the substrate and having pad regions extended further at edge portions of the conductive patterns as the conductive patterns descend from an uppermost conductive pattern to a lowermost conductive pattern, a first contact plug disposed on a first pad region of the lowermost conductive pattern, a buffer conductive pattern disposed on a second pad region positioned above the first pad region, and a second contact plug formed on the buffer conductive pattern.

Contact structure and manufacturing method thereof

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Seoul, South Korea

Gwang-Hyun Baek