Skhynix Inc.

Gwan Woo Kim

Eun Ji Choi

Soon Sung An

Sung Hwa Ok

Keun Seon Ahn

In Seok Kong

Jae Hyeong Hong

Jun Seo Jang

Kwan Su Shon

Yo Han Jeong

Jae Young Park

Sun Ki Cho

Bon Kwang Koo

Jaehyeong Hong

Dong Wook Jang

Junseo Jang

Heon Ki Kim

Beom Kyu Seo

Daeho Yang

Jung Yeop Lee

Ji Young Lee

A receiver circuit includes an input unit configured to receive a reception pattern signal in a training mode, and a reception normal signal in a normal mode, an enable control unit configured to determine whether to activate an enable signal according to the reception pattern signal in the training mode, a first decision feedback equalizer configured to operate in an activation period of the enable signal, and to remove a first post-cursor component for the reception normal signal by calibrating a currently received value based on a previously received value of the reception normal signal, and a second decision feedback equalizer configured to, when the enable signal is in an activated state, remove second to Npost-cursor components for the reception normal signal by adjusting driving abilities of input transistors, to which the currently received value is applied, according to patterns of the reception normal signal.

Receiver circuit and operation method for the same

A voltage generation circuit includes a voltage generation unit configured to generate a reference voltage using a power supply voltage and output the reference voltage through a voltage output node. The voltage generation circuit also includes a pre-charge unit configured to drive the voltage output node using the power supply voltage in response to a pre-charge control signal. The voltage generation circuit further includes a pre-charge control unit configured to generate at least one sampling voltage using the power supply voltage and generate the pre-charge control signal according to a result obtained by comparing the at least one sampling voltage with the reference voltage.

Pre-charge control circuit and voltage generation circuit including the same

The present disclosure relates to a memory device for correcting a pulse duty ratio and a memory system including the same, and relates to a memory device which corrects the duty ratio of a primary pulse of a memory device control signal, and a memory system including the same.

Memory device for correcting pulse duty and memory system including the same

Growing community of inventors

Icheon-si, South Korea

Gwan Woo Kim