Taiwan Semiconductor Manufacturing Comp. Ltd.

Gwan Sin Chang

Kuo-Cheng Ching

Zhiqiang Wu

Chih-Hao Wang

Carlos H Diaz

Jean-Pierre Colinge

Lee-Chung Lu

Yi-Kan Cheng

Wen-Ju Preet Yang

Ru-Gun Liu

Li-Chun Tien

Yuan-Te Hou

Huang-Yu Chen

Ke-Ying Su

Chung-Te Lin

Ping-Wei Wang

Tsai-Sheng Gau

Ken-Hsien Hsieh

Wen-Chun Huang

Yung-Sung Yen

Feng-Ming Chang

Chien-Wen Chen

Ming-Hui Chih

Yen-Sen Wang

Cliff Hou

Cheng-Hung Yeh

Chia-Ming Ho

Pi-Tsung Chen

Chih-Tsung Yao

Wei-Long Wang

Yao-Jen Chuang

Fung Song Lee

Chih-Ming Lai

Kong-Beng Thei

Chung-Hsing Wang

Shi Ning Ju

Harry Chuang

Sheng-Chen Chung

Yung-Chin Hou

Zhe-Wei Jiang

Jung-Hui Kao

Chung Long Cheng

Mong Song Liang

Gary Shen

Chun-Hui Tai

Chun Chung Su

Ping Chung Li

Jill Liu

Ivy Chiu

Hsiao-Shu Chiao

Cheng Hung Yeh

A Fin Field-Effect Transistor (FinFET) includes a semiconductor layer over a substrate, wherein the semiconductor layer forms a channel of the FinFET. A first silicon germanium oxide layer is over the substrate, wherein the first silicon germanium oxide layer has a first germanium percentage. A second silicon germanium oxide layer is over the first silicon germanium oxide layer. The second silicon germanium oxide layer has a second germanium percentage greater than the first germanium percentage. A gate dielectric is on sidewalls and a top surface of the semiconductor layer. A gate electrode is over the gate dielectric.

Tuning strain in semiconductor devices

A vertical Metal-Oxide-Semiconductor (MOS) transistor includes a substrate and a nano-wire over the substrate. The nano-wire comprises a semiconductor material. An oxide ring extends from an outer sidewall of the nano-wire into the nano-wire, with a center portion of the nano-wire encircled by the oxide ring. The vertical MOS transistor further includes a gate dielectric encircling a portion of the nano-wire, a gate electrode encircling the gate dielectric, a first source/drain region underlying the gate electrode, and a second source/drain region overlying the gate electrode. The second source/drain region extends into the center portion of the nano-wire. Localized oxidation produces a local swelling in the structure that generates a tensile or compressive strain in the nano-wire.

Method for inducing strain in vertical semiconductor columns

A method includes performing a first epitaxy to grow a silicon germanium layer over a semiconductor substrate, performing a second epitaxy to grow a silicon layer over the silicon germanium layer, and performing a first oxidation to oxidize the silicon germanium layer, wherein first silicon germanium oxide regions are generated. A strain releasing operation is performed to release a strain caused by the first silicon germanium oxide regions. A gate dielectric is formed on a top surface and a sidewall of the silicon layer. A gate electrode is formed over the gate dielectric.

Thermally tuning strain in semiconductor devices

A semiconductor chip includes a row of cells, with each of the cells including a VDD line and a VSS line. All VDD lines of the cells are connected as a single VDD line, and all VSS lines of the cells are connected as a single VSS line. No double-patterning full trace having an even number of Gpaths exists in the row of cells, or no double-patterning full trace having an odd number of Gpaths exists in the row of cells.

Methods for double-patterning-compliant standard cell design

Methods are disclosed herein for fabricating integrated circuit devices, such as fin-like field-effect transistors (FinFETs). An exemplary method includes forming a first semiconductor material layer over a fin portion of a substrate; forming a second semiconductor material layer over the first semiconductor material layer; and converting a portion of the first semiconductor material layer to a first semiconductor oxide layer. The fin portion of the substrate, the first semiconductor material layer, the first semiconductor oxide layer, and the second semiconductor material layer form a fin. The method further includes forming a gate stack overwrapping the fin.

FinFET device and method for fabricating same

A device includes a semiconductor substrate and a vertical nano-wire over the semiconductor substrate. The vertical nano-wire includes a bottom source/drain region, a channel region over the bottom source/drain region, and a top source/drain region over the channel region. A top Inter-Layer Dielectric (ILD) encircles the top source/drain region. The device further includes a bottom ILD encircling the bottom source/drain region, a gate electrode encircling the channel region, and a strain-applying layer having vertical portions on opposite sides of, and contacting opposite sidewalls of, the top ILD, the bottom ILD, and the gate electrode.

Inducing localized strain in vertical nanowire transistors

The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having isolation regions, a gate region, source and drain regions separated by the gate region, a first fin structure in a gate region. The first fin structure includes a first semiconductor material layer as a lower portion of the first fin structure, a semiconductor oxide layer as an outer portion of a middle portion of the first fin structure, the first semiconductor material layer as a center portion of the middle portion of the first fin structure and a second semiconductor material layer as an upper portion of the first fin structure. The semiconductor device also includes a source/drain feature over the substrate in the source/drain region between two adjacent isolation regions and a high-k (HK)/metal gate (MG) stack in the gate region, wrapping over a portion of the first fin structure.

FinFET device and method of fabricating same

The present disclosure relates to a Fin field effect transistor (FinFET) device having a buried silicon germanium oxide structure configured to enhance performance of the FinFET device. In some embodiments, the FinFET device has a three-dimensional fin of semiconductor material protruding from a substrate at a position located between first and second isolation regions. A gate structure overlies the three-dimensional fin of semiconductor material. The gate structure controls the flow of charge carriers within the three-dimensional fin of semiconductor material. A buried silicon-germanium-oxide (SiGeOx) structure is disposed within the three-dimensional fin of semiconductor material at a position extending between the first and second isolation regions.

Buried SiGe oxide FinFET scheme for device enhancement

The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having a gate region, source and drain (S/D) regions separated by the gate region and a first fin structure in a gate region in the N-FET region. The first fin structure is formed by a first semiconductor material layer as a lower portion, a semiconductor oxide layer as a middle portion and a second semiconductor material layer as an upper portion. The semiconductor device also includes a second fin structure in S/D regions in the N-FET region. The second fin structure is formed by the first semiconductor material layer as a lower portion and the semiconductor oxide layer as a first middle portion, the first semiconductor material layer as a second middle portion beside the first middle and the second semiconductor material layer as an upper portion.

Semiconductor device and fabricating the same

A method includes determining one or more potential merges corresponding to a color set Aand a color set Aof N color sets, represented by Ato A, used in coloring polygons of a layout of an integrated circuit. N is a positive integer, i and j are integers from 1 to N, and i&#x2260;j. One or more potential cuts corresponding to the color set Aand the second color set Aare determined. An index Ais determined according to the one or more potential merges and the one or more potential cuts. A plurality of parameters F related to the index Ais obtained based on various values of indices fand f. A parameter F is selected among the plurality of parameters F based on a definition of the index A.

Method of merging color sets of layout

A semiconductor chip includes a row of cells, with each of the cells including a VDD line and a VSS line. All VDD lines of the cells are connected as a single VDD line, and all VSS lines of the cells are connected as a single VSS line. No double-patterning full trace having an even number of G0 paths exists in the row of cells, or no double-patterning full trace having an odd number of G0 paths exists in the row of cells.

Growing community of inventors

Hsin-Chu, Taiwan

Gwan Sin Chang