The Texas A&m University System

Gwan Seong Choi

Kiran Kumar Gunnam

Sina Pourjabar

A method and system for decoding low density parity check (LDPC) codes. An LDPC code decoder includes LDPC decoding circuitry comprising a Q message generator and a P sum adder array. The Q message generator combines an R message from a previous iteration with a P message to produce a Q message. The P sum adder array adds the P message to a difference of an R message from a current iteration and the R message from the previous iteration to produce an updated P message.

Low density parity check decoder

A method and system for decoding low density parity check ('LDPC') codes. An LDPC code decoder includes LDPC decoding circuitry comprising a Q message generator and a P sum adder array. The Q message generator combines an R message from a previous iteration with a P message to produce a Q message. The P sum adder array adds the P message to a difference of an R message from a current iteration and the R message from the previous iteration to produce an updated P message.

A method includes receiving a first data frame and a second data frame from a communication channel; decoding the first data frame using a first portion of an extended parity-check matrix (PCM); and decoding the second data frame using a second portion of the extended PCM. The first portion is a subset of the second portion.

Variable rate low density parity check decoder

A method and system for decoding low density parity check ('LDPC') codes. A method and system for decoding low density parity check ('LDPC') codes. An LDPC code decoder includes decoding circuitry configured to process blocks of an LDPC matrix. The decoding circuitry includes a control unit that controls processing by the decoding circuitry. The control unit is configured to cause the decoding circuitry to process blocks of a layer of the LDPC matrix out of order.

A method and system for decoding low density parity check ('LDPC') codes. An LDPC decoder includes an R select unit, a Q message first-in first-out ('FIFO') memory, and a cyclic shifter. The R select unit provides an R message by selecting from a plurality of possible R message values. The Q message memory stores a Q message until an R message is generated by a CNU, the Q message and the R message are combined to provide a P message. The cyclic shifter shifts the P message.

Low density parity check decoder for regular LDPC codes

A method and system for decoding low density parity check ('LDPC') codes. An LDPC decoder includes a control unit that controls decoder processing, the control unit causing the decoder to process the blocks of a low density parity check ('LDPC') matrix out of order. A decoder embodiment may process the layers of the LDPC matrix out of order and/or perform partial state processing on out of order blocks of the LDPC matrix and/or generate R messages out of order.

Growing community of inventors

College Station, TX, United States of America

Gwan Seong Choi