Samsung Electronics Co., Ltd.

Gwan-Hyeob Koh

Dae-Hwan Kang

Ji-Hyun Jeong

Dae-Shik Kim

Yoon-jong Song

Ki-seok Suh

Su-Jin Ahn

Dae-Won Ha

Kil-Ho Lee

Kyu-Rie Sim

Yoon-Jong Song

Jae-Chul Shim

Jae-Goo Lee

Jin-Woo Lee

Jae-kyu Lee

Yong-kyu Lee

Jung-Hoon Bak

Yoo-Sang Hwang

Jeong-Heon Park

Bong-jin Kuh

Se-Ho Lee

Hyeong-sun Hong

Chang-hyun Cho

Young-Nam Hwang

Sung-lae Cho

Kyung-Chang Ryoo

Masayuki Terai

Chang-Wook Jeong

Sung-woo Kim

Bo-young Seo

Su-Youn Lee

Yong-Seok Chung

Il-mok Park

Myoung-Su Son

Jang-Eun Lee

Yong-Ho Ha

Ji-Hye Yi

Suk-Soo Pyo

Soon-Oh Park

Yoonjong Song

Sang-Don Nam

Jung Hyuk Lee

Kwang-woo Lee

Hyoung-Joon Kim

Choong-Man Lee

Seung Pil Ko

Shinhee Han

Hong-kook Min

Myoungsu Son

Sung-Jin Kim

Ki-Nam Kim

Yong-Jae Kim

Tae-Young Chung

Woo-Jin Kim

Chang-Hyun Cho

Ju-Wan Kim

Choong-jae Lee

Dae-Eun Jeong

Byung-Keun Hwang

Mi-hyang Lee

Song-yi Kim

Mina Lee

Jue-Goo Lee

In a method of manufacturing an MRAM device, first and second lower electrodes may be formed on first and second regions, respectively, of a substrate. First and second MTJ structures having different switching current densities from each other may be formed on the first and second lower electrodes, respectively. First and second upper electrodes may be formed on the first and second MTJ structures, respectively.

Semiconductor device, magnetoresistive random access memory device, and semiconductor chip including the same

A complementary metal-oxide semiconductor (CMOS) image sensor (CIS) with a simplified stacked structure and improved operation characteristics includes an upper chip, in which a plurality of pixels are arranged in a two-dimensional array structure, and a lower chip below the upper chip including a logic region having logic circuits and a memory region having embedded therein magnetic random access memory (MRAM) used as image buffer memory for storing image data processed by the logic region.

Image sensor including MRAM (magnetic random access memory)

An integrated circuit (IC) device may include a single substrate that includes a single chip, and a plurality of memory cells spaced apart from one another on the substrate and having different structures. Manufacturing the IC device may include forming a plurality of first word lines in a first region of the substrate, and forming a plurality of second word lines in or on a second region of the substrate. Capacitors may be formed on the first word lines. Source lines may be formed on the second word lines. An insulation layer that covers the plurality of capacitors and the plurality of source lines may be formed in the first region and the second region. A variable resistance structure may be formed at a location spaced apart from an upper surface of the substrate by a first vertical distance, in the second region.

Integrated circuit devices and methods of manufacturing same

In a method of manufacturing an MRAM device, a memory unit including a lower electrode, an MTJ structure and an upper electrode sequentially stacked is formed on a substrate. A protective layer structure including a capping layer, a sacrificial layer and an etch stop layer sequentially stacked is formed on the substrate to cover the memory unit. An insulating interlayer is formed on the protective layer structure. The insulating interlayer is formed to form an opening exposing the protective layer structure. The exposed protective layer structure is partially removed to expose the upper electrode. A wiring is formed on the exposed upper electrode to fill the opening.

Magnetoresistive random access memory device and method of manufacturing the same

Provided are a memory device and a method of manufacturing the same. Memory cells of the memory device are formed separately from first electrode lines and second electrode lines, wherein the second electrode lines over the memory cells are formed by a damascene process, thereby avoiding complications associated with CMP being excessively or insufficiently performed on an insulation layer over the memory cells.

Memory cell and memory device comprising selection device layer, middle electrode layer and variable resistance layer

A memory system includes a memory cell array including a first memory area and a second memory area, an input/output circuit including input/output lines for transmitting or receiving data bits and parity bits to or from the first and second memory areas, and an error correction circuit including a plurality of sub error correction circuits including a first sub error correction circuit for performing a first error correction operation on first data bits of the first memory area received through the input/output lines, and a second sub error correction circuit for performing a second error correction operation on second data bits of the second memory area received through the input/output lines. The first memory area has a higher bit error rate than the second memory area.

Memory device and memory system having multiple error correction functions, and operating method thereof

A semiconductor device includes a gate structure on a substrate, source and drain contacts respectively on opposite sides of the gate structure and connected to the substrate, a magnetic tunnel junction connected to the drain contact, a first conductive line connected to the source contact, and a second conductive line connected to the first conductive line through a first via contact. The second conductive line is distal to the substrate in relation to the first conductive line. The first and second conductive lines extend in parallel along a first direction. The first and second conductive lines have widths in a second direction intersecting the first direction. The widths of the first and second conductive lines are the same. The first via contact is aligned with the source contact along a third direction perpendicular to a top surface of the substrate.

Semiconductor devices

A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer. The first memory cell has a side surface slope so as to have a width gradually decreasing toward its upper portion.

Memory device and method of manufacturing the same

A semiconductor device may include a conductive structure on a substrate, a contact plug on the conductive structure, and a magnetic tunnel junction structure on the contact plug. A lower surface of the contact plug may have an area greater than that of an upper surface thereof, and the contact plug may include a capping pattern at least partially covering an upper surface of the conductive structure, a conductive pattern on the capping pattern, and an amorphous metal pattern on the conductive pattern.

Integrated circuit devices

Magnetoresistive random access memory device

Growing community of inventors

Seoul, South Korea

Gwan-Hyeob Koh