Altera Corporation

Klp International, Ltd.

Guy R Schlacter

Martin Langhammer

Ali H Burney

Gregory R Steinke

Bernd Neidermeier

Various techniques for controlling use of configuration data for and/or a design implemented as user logic in a configurable PLD (programmable logic device) include programming the configurable PLD using configuration data provided by a secure device. The programmed configurable PLD includes user logic, a configurable device authorization code generator and a comparator. The user logic is immediately disabled after it is loaded into the configurable device. A configurable device authorization code is generated in the configurable device authorization code generator in the programmed configurable PLD and is sent to the comparator. A secure device authorization code is generated by a secure device authorization code generator and also is sent to the comparator. The comparator compares the two inputs and, if the configurable device authorization code and secure device authorization code are identical, the user logic is then enabled. The configurable device authorization codes and secure device authorization codes may be generated in various ways, including using pseudo-random number generators, encryptors and/or decryptors in combination in the configurable device and the secure device. Various apparatus for implementing the present invention include a secure device configured to generate a secure device signal on which the secure device authorization code is based and a configuration data storage which provides programming instructions for controlling use of configuration data that generates the user logic and required functionalities in the configurable device.

Method and apparatus for protecting designs in SRAM-based programmable logic devices

An interface receiver, which is part of an interface that allows the transfer of data between two incompatible I/O standards, includes a crossbar and a barrel shifter that can be implemented using multiplier-accumulator blocks. The crossbar reorders an incoming burst of data and writes the data into a larger data column where the data is barrel-shifted using multiplier-accumulator blocks and transferred out of the receiver when an end-of-packet is detected or the shifted data column as seen from outside the interface receiver is full.

Implementing crossbars and barrel shifters using multiplier-accumulator blocks

The embodiments of the present invention relate to the general area of the Field Programmable Gate Arrays, and, in particular to the architecture and the structure of the building blocks of the Field Programmable Gate Arrays. The proposed logic units, as separate units or cluster of units, which are mainly comprised of look-up tables, multiplexers, and a latch, implement functions such as addition, subtraction, multiplication, and can perform as shift registers, finite state machines, multiplexers, accumulators, counters, multi-level random logic, and look-up tables, among other functions. Having two outputs, the embodiments of the logic unit can operate in split-mode and perform two separate logic and/or arithmetic functions at the same time. Clusters of the proposed logic units, which utilize local interconnections instead of traditional routing channels, add to efficiency, speed, and reduce required real estate.

Field programmable gate array logic unit and its cluster

The embodiments of the present invention relate to the general area of Field Programmable Gate Arrays and, in particular, to Field Programmable Gate Arrays ('FPGAs') comprising memory cells with both volatile and nonvolatile properties, and the control and management of each portion to overcome the disadvantages of each individual technology. Some of the advantages of combining the two properties in a single FPGA are power reduction, shorter power-on time, configuration flexibility, instant-on logic capability, cost savings in system components including nonvolatile instant-on devices, configuration memories, and standard CMOS process. Furthermore, to optimize these and other advantages of the proposed architecture, additional apparatus and methods are presented to individually and collectively manage and control different parts of such hybrid FPGAs.

Field programmable gate arrays using both volatile and nonvolatile memory cell properties and their control

Methods are provided for helping to automate the design of electronic circuitry in which multiple memory functions are provided by common physical memory. Interactive computer screens prompt the user to enter information about the multiple memory functions that the user desires. The data thus entered by the user is then reformatted for use as specific values of parameters in a parameterized function that can provide the required circuit design when its parameters are thus supplied with specific values.

Logic generation for multiple memory functions

Circuitry that includes blocks of memory can be used to emulate a content addressable memory (&ldquo;CAM&rdquo;). The CAM data is stored in enough blocks of memory so that all of that data can be gradually read out in the time allowed for completion of a CAM search. As the data is read out, it is compared to CAM search data. If and when a match is found, a CAM address associated with the CAM data found to match the search data is generated. Alternatively or in addition, a simple &ldquo;match&rdquo; signal may be generated. If desired, the contents of the emulated CAM may be changed. To do this, circuitry is provided for converting the CAM address of the new data to an appropriate physical address (in the above-mentioned memory blocks) for that data.

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Buffalo Grove, IL, United States of America

Guy R Schlacter