Intel Corporation

Guy Peled

Zeev Sperber

Doron Orenstein

Ehud Cohen

Robert Valentine

Doron Orenstien

Gabi Malka

Oded Lempel

Guillermo Savransky

Ilan Y Spillinger

Guiliermo Savranski

A memory system is provided for storing multiple data types. The memory system includes a main memory, a local cache, and a translation unit. The local cache has multiple entries, each of which includes a data field to store data and a status field to indicate a storage state for the stored data. The translation unit includes a translation lookaside buffer (TLB) and a status-cache (STC). The TLB stores address translations for data in the main memory, and the STC stores storage states for data indicated by the address translations.

Memory system for multiple data types

The present invention provides a mechanism for implementing z-compression in a manner that is transparent to the user. Blocks of z-data are associated with storage locations in a z-data buffer in cleared, compressed, or uncompressed data states. Operations to the z-data buffer are monitored for selected operations. These operations may include clear or lock operations. If a selected operation is detected, a modified version of the selected operation is implemented to mask differences between the storage states of the data blocks.

Mechanism for implementing Z-compression transparently

A graphics system is provided to implement compression of depth or z-data. The graphic system includes a buffer, a status table, and a read/write unit. The buffer stores depth data for multiple blocks of pixels in associated buffer entries. The status table stores status values for the entries of the buffer. The status value for a given entry indicates an access mode for the corresponding depth data according to whether the data is compressed, uncompressed or in a reference state. The read/write unit implements data accesses for a given entry responsive to the status value associated with the entry.

Z-compression mechanism

A cache memory includes a data array and a trace victim cache. The data array is adapted to store a plurality of trace segments. Each trace segment includes at least one trace segment member. The trace victim cache is adapted to store plurality of entries. Each entry includes a replaced trace segment member selected for replacement from one of the plurality of trace segments. A method for accessing cached instructions, the cached instructions being stored in a data array, the cached instructions being organized in trace segments, the trace segment having a plurality of trace segment members, includes retrieving a first trace segment member of a first trace segment; identifying an expected location within the data array of at least one subsequent trace segment member of the first trace segment; determining if the subsequent trace segment member is stored in the data array at the expected location; and determining if the subsequent trace segment member is stored in a trace victim cache if the subsequent trace segment member is not stored in the data array at the expected location.

Trace victim cache

An apparatus includes a data array, control logic, an entry candidate table, and a future target table. The control logic is coupled to the data array and adapted to store at least one trace segment of instructions into the data array. The entry candidate table is coupled to the control logic and is adapted to store offset information related to the position of a selected instruction within the trace segment. The future target table is coupled to the control logic and adapted to store a potential entry point into the trace segment. A method for caching instructions includes storing a first plurality of instructions in a first trace segment. A control flow instruction is identified from the first plurality of instructions and the outcome of the control flow instruction is predicted. The control flow instruction has a predicted taken target address and a predicted not-taken target address corresponding to the outcome predicted. The predicted not-taken target address is stored.

Method and apparatus for identifying potential entry points into trace

An apparatus includes a data array and control logic. The control logic is coupled to the data array and adapted to store at least one trace segment of instructions into the data array. The control logic allows the instructions of the trace segment to be sequentially retrieved beginning with a selected instruction. The selected instruction is offset from the first instruction of the trace segment. A method for caching instructions includes storing a first plurality of instructions in a first trace segment. A selected instruction of the first plurality of instructions is identified within the first trace segment. The selected instruction is offset from the first instruction of the first trace segment. The offset information related to the position of the selected instruction within the first trace segment is stored. A method for retrieving cached instructions, wherein the cached instructions are stored in a trace segment and the trace segment has a head instruction, includes determining a linear address related to a selected instruction to be retrieved. An entry point into the trace segment corresponding to the linear address is identified. The entry point is offset from the head instruction. The selected instruction is retrieved from the entry point within the identified trace segment.

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Yokneam, Israel

Guy Peled