Amazon Technologies, Inc.

Marvell Israel (misl) Ltd.

Other

Guy Nakibly

Nafea Bshara

Erez Izenberg

Adi Habusha

Georgy Machulsky

Leah Shalev

Yaniv Shapira

Ofer Frishman

Uri Leder

Ron Diamant

Moshe Raz

Benzi Denkberg

Barak Wasserstrom

Dan Ilan

Roi Ben Haim

Daniel Joseph Grey

Zvika Glaubach

Dan Saad

Matthew Shawn Wilson

Saar Gross

Jonathan Cohen

Itay Poleg

Usama Nassir

Eilon Argov

Said Bshara

Avigdor Segal

Itai Avron

Rabeeh Khoury

Sergey Kleyman

Se Wang Oh

Simaan Bahouth

Max Chvalevsky

Ori Ariel

Lev Vaskevich

Ariel Pescovsky

Muhamad Grefat

Gal Avisar

Barak Singer

Rashika Kheria

Moshe Noah

Aviv Bonomo

Dror Fleischmann

Moshe Gutman

Apparatus and methods are disclosed herein for remote, direct memory access (RDMA) technology that enables direct memory access from one host computer memory to another host computer memory over a physical or virtual computer network. In one example, RDMA functionality is provided by combining a host executing instructions for RDMA software applications with dedicated hardware accelerator, where the host has access to substantially all RDMA connection context (e.g., configuration, status, state machine, counters, etc.) and a hardware accelerator stores a portion of the context information for a set of currently active transactions. The hardware accelerator derives a transaction identifier from header information in received RDMA packets and performs a local RDMA operation using at least a portion of the received data, a destination address of the location RDMA operation being based at least in part on a memory address determined using the transaction identifier.

Transaction based remote direct memory access

Apparatus and methods are disclosed herein for remote, direct memory access (RDMA) technology that enables direct memory access from one host computer memory to another host computer memory over a physical or virtual computer network according to a number of different RDMA protocols. In one example, a method includes receiving remote direct memory access (RDMA) packets via a network adapter, deriving a protocol index identifying an RDMA protocol used to encode data for an RDMA transaction associated with the RDMA packets, applying the protocol index to a generate RDMA commands from header information in at least one of the received RDMA packets, and performing an RDMA operation using the RDMA commands.

Flexible remote direct memory access

A wake-up management circuit for implementation in circuit boards with multiple processors is disclosed. The wake-up management circuit utilizes hardware resources to generate a wake-up signal for a processor in a low power mode when traffic intended for the processor is received by the wake-up management circuit. The wake-up management circuit is configured to generate a wake-up signal for a specific processor when address information in a data packet received by the wake-up management circuit indicates that the data packet is intended for the specific processor (e.g., the specific processor is the destination for the data packet).

Wake-up management circuit for multiple processors

A link layer reliability (LLR) circuit of a communication device can receive an indication that a link down event has occurred on a bus link with a peer device. The LLR circuit can prevent the link down event from triggering a reset of configuration registers containing bus settings for the bus link. Once the bus link has been restored, the LLR circuit can send a retry request to the peer device indicating an expected sequence number associated with a transaction that the LLR circuit is expecting from the peer device. The LLR circuit may receive a retry acknowledgment from the peer device indicating receipt of the retry request for the transaction corresponding to the expected sequence number, and payload data for the transaction corresponding to the expected sequence number.

Link down resilience

Techniques for cooperative timing alignment using synchronization pulses are described. The techniques can include generating, at an integrated circuit device, a timing signal, controlling a local count value based on the timing signal, monitoring a synchronization signal of a system comprising the integrated circuit device, detecting a synchronization pulse in the synchronization signal, and aligning the local count value with an implied count value associated with the synchronization pulse in order to align the local count value with those of other integrated circuit devices of the system.

Security protection for synchronization pulses

An address decoder for a system is disclosed that can be used for different source nodes in the system. Each address decoder can be configured to perform a plurality of decode methods that can be customized for each source node. A first decode method can be used to determine a target node from a plurality of target nodes based on a destination address of the transaction. A second decode method can be used to assign a dedicated target node as the target node irrespective of the destination address of the transaction. The second decode method can be used to route the transaction to the dedicated target node for testing and verification operations.

Configurable address decoder

System halt support for synchronization pulses

Techniques are provided to maintain data coherency for data transfers among data processing devices in a distributed computing environment. A data buffer in each data processing device can be mapped to an address range that is assigned to transactions that allow out-of-order completions, and a message buffer in each data processing device can be mapped to an address range that is assigned to transactions that follow transaction ordering. Thus, a transaction to store a set of data into the data buffer is completed before a transaction to write a synchronization message in the message buffer indicating that the set of data is stored in the data buffer based on the mapping irrespective of the transaction ordering indicated by each transaction.

Transaction ordering based on target address

A first configurable address decoder can be coupled between a source node and a first interconnect fabric, and a second address decoder can be coupled between the first interconnect fabric and a second interconnect fabric. The first address decoder can be configured with a first address mapping table that can map a first set of address ranges to a first set of target nodes connected to the first interconnect fabric. The second address decoder can be configured with a second address mapping table that can map a second set of address ranges to a second set of target nodes connected to the second interconnect fabric. The second address decoder can be part of the first set of target nodes. The first address decoder and the second address decoder can be configured or re-configured to determine different routes for a transaction from the source node to a target node in the second set of target nodes via the first and second interconnect fabrics.

Configurable routing in a multi-chip system

Cooperative timing alignment using synchronization pulses

Techniques are described for maintaining in-order execution when a dependency exists between write transactions. In some embodiments, a write re-order buffer (WROB) is configured to assign the same group ID to an incoming write transaction upon determining that the incoming write transaction is dependent on a pending write transaction. The WROB forwards the incoming write transaction to an interconnect fabric for routing to a completer device. The interconnect fabric enforces in-order execution when write transactions share the same group ID. The WROB can maintain a transaction log of pending write transactions and also track the statuses of responses for such transactions. Transaction responses can include responses sent from a completer to confirm that a transaction has actually been completed. Additionally, the WROB can send a response indicating completion back to the requester of the transaction. In some embodiments, the WROB is configured to send an early response to the requester.

Re-order buffer for in-order execution of dependent write transactions

Techniques for emulating a configuration space may include emulating a set of configuration registers for a set of functions corresponding to a type of peripheral device. The set of functions can include a physical function and a virtual function associated with the physical function. A configuration access request can be processed by retrieving an emulated configuration register from the emulated configuration space, and logging incoming configuration access requests in a configuration transaction log to track configuration accesses.

Emulated endpoint configuration

A coherent connection and a non-coherent connection are provided between system-on-chips (SoCs). The coherent connection can be coupled to coherent interconnects on the SoCs, and the non-coherent connection can be coupled to non-coherent interconnects on the SoCs. An input/output (I/O) transaction from an I/O device on a first SoC that is targeted to a second SoC can be transmitted via the non-coherent connection, and a processor transaction from the first SoC that is targeted to the second SoC can be transmitted via the coherent connection.

Non-coherent and coherent connections in a multi-chip system

A write cleaner circuit can be used to implement write-through (WT) functionality by a write-back (WB) cache memory for updating the system memory. The write cleaner circuit can intercept memory write transactions issued to the WB cache memory and generate clean requests that can enable the WB cache memory to send update requests to corresponding memory locations in the system memory around the same time as the memory write transactions are performed by the WB cache memory, and clear dirty bits in the cache lines corresponding to those memory write transactions.

Clean engine for write-back cache memory

Growing community of inventors

Kedumim, Israel

Guy Nakibly