Sun Microsystems, Inc.

Guy Moffat

Curtis R Priem

Chris A Malachowsky

Bruce McIntyre

Michael G Lavelle

Satyanarayana Nishtala

Daniel E Lenoski

Thomas P Webber

Peter A Mehring

Christopher R Owen

A computer system with a multiplexed address bus that is shared by both system memory and by slave devices is described. The slave devices are incorporated into an existing system memory configuration by providing a bus controller to execute a two-cycle address sequence on the multiplexed address bus. The address sequence is followed by a transfer of data. A random latency can exist between the time of receiving address information and the time of receiving data corresponding to the address information. This random latency can be exploited by the system CPU for other computational purposes. The bus controller of the system executes multiple, or pipelined, data writes to the bus before an acknowledgement for the first data write is received. In this scheme, the acknowledgement for the first data write is typically sent during the same time period that the subsequent data writes are being received. Consequently, data transfer acknowledgements overlap data writes. This overlapping operation allows the bus to be completely utilized during write operations, thereby improving data bandwidth.

Computer system with a shared address bus and pipelined write operations

An arrangement providing frame buffer memory for an output display by which single buffer and double buffered application programs may be run singly or simultaneously is described. An array of video random access memory sufficient to store data for at least two complete frames is configured in three different ways depending on the applications being run. When only programs designed to run on a single frame buffer are run, the memory is configured as a single frame buffer. When a single program designed to run on double frame buffers is run, the memory is configured as two visible frame buffers. When multiple programs designed to run on double frame buffers are run, the memory is configured into one visible and one invisible frame buffer. Additionally, apparatus for selecting data to be furnished to the display depending on whether the program operates as a single buffered program, a double buffered program, or a plurality of double buffered programs is provided.

Method and apparatus for providing a configurable display memory for

An output display system including an output display; apparatus for controlling the writing of information to the output display; and a double buffered memory including a first bank of video random access memory for furnishing information to the output display, a second bank of video random access memory for furnishing information to the output display, and apparatus for addressing alternate banks of memory as each line of the output display in a frame is written.

Method and apparatus for increasing the speed of operation of a double

An arrangement for assuring the compatibility of versions of software produced for a particular computer hardware architecture including a hardware version register, apparatus for providing an indication of a version of hardware being utilized to operate a particular version of software, a software version register, apparatus for providing an indication of a version of software being run on the particular version of hardware, apparatus for comparing the version of hardware and the version software, and apparatus responsive to the results of the comparison for setting defaults and enabling circuitry in the hardware so that the version of software runs correctly on the version of hardware.

Method and apparatus for allowing computer circuitry to function with

A double buffered output display system including a first frame buffer, a second frame buffer, a multiplexor for furnishing data to an output display from one of the first or the second frame buffers, apparatus for storing a signal indicating that the multiplexor is to select a different frame buffer to furnishing data to an output display, and apparatus for furnishing the stored signal to the multiplexor only at the completion of a frame on a display and before a new frame commences.

Apparatus for selecting frame buffers for display in a double buffered

An arrangement for writing to and reading from the random access ports of a multibank frame buffer so that individual pixels to be presented in a vertical line on an output display are arranged sequentially from top to bottom in different banks of the frame buffer.

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Palo Alto, CA, United States of America

Guy Moffat