Hewlett-Packard Development Company, L.p.

Guy Lowell Kuntz

Ken Gary Pomaranski

Stephen Patrick Hack

Howard Calkin

Jeff Barlow

Lacey Joyal

Jeff Brauch

Michael Christopher Sedmak

Raymond Gratias

Ryan Lee Weaver

Paul Bouchier

Richard Dickert Powers

Gary Belgrave Gostin

Mark Edward Shaw

Vipul Gandhi

Ronald E Gilbert, Jr

Gregg Bernard Lesartre

Andrew Christopher Walton

Craig William Warner

Stephen J Silva

Bryan Stephenson

Steven T Roth

David Paul Hannum

Todd J Kjos

Brian Matthew Johnson

Larry N McMahan

Brendan A Voge

Glen Edwards

Michael Sedmark

Aron Charles Miller

David Matthew Bellia

Leon Hong

James E Kleeb

Ray Gratias

In one embodiment, a cache element allocation method is provided. Each cache element on a CPU is assigned a quality rank based on the error rate of the cache element. If an allocated cache element is deemed to be faulty, the quality rank of the faulty allocated cache element is compared with the quality rank of the non-allocated cache elements. If a non-allocated cache element has a lower quality rank than the allocated cache element, the non-allocated cache element is swapped in for the allocated cache element.

Systems and methods for CPU repair

In one embodiment, a CPU cache management system is provided. The CPU management system includes, for example, a CPU chip and cache management logic. The CPU chip include cache elements that are initially in use and spare cache elements that not initially in use. The cache management logic determines whether currently-used cache elements are faulty. If a cache element is determined to be faulty, the cache management logic schedules a reboot of the computer and swaps in a spare cache element for the faulty currently-used cache element during the reboot.

Routes between cells in an interconnection network are represented with a graph using graph theory. Failed links are identified, and using the graph, alternative routes between cells in the graph are found.

Network graph for alternate routes

Systems and methods for repairing a processor are provided. In one embodiment, a method for repairing a processor is provided that includes, for example, the steps of initializing and executing an operating system, determining that a cache element is faulty, and swapping in a spare cache element for said faulty cache element while the operating system is executing.

Systems and methods for conducting processor health-checks are provided. In one embodiment, a method for evaluating the status of a processor is provided. The method includes, for example, initializing and executing an operating system, de-allocating the processor from the available pool or system resources and performing a health-check on the processor while the operating system is executing.

Methods and systems for conducting processor health-checks

In one embodiment, a method for repairing a faulty cache element is provided. Once a monitored cache element is determined to be faulty, the system stores the repair information, and cache configuration in an EEPROM or non-volatile memory on the CPU module. Then the computer is rebooted. During the reboot, the faulty cache element is repaired by being swapped out for a spare cache element based on the information stored in the EEPROM or the non-volatile memory.

The inventive multiple partition computer system allows the reconfiguration of the installed hardware, possibly while the various partitions continue normal operations. This aspect includes adding and removing process cell boards and I/O from partitions which may or may not continue to run. The invention also allows changes to the association between cells, I/O and partitions. The partitions may be able to stay running, or may have to be shut down from the resulting changes. In the invention, multiple copies of the OS are running independently of each other, each in a partition that has its own cell boards with processors and memory and connected I/O. This provides isolation between different applications. Consequently, a fatal error in one partition would not affect the other partitions. A network of micro-controllers connected to a service processor, via a communications link, provides the service processor with information on each of the different cells, as well as a pathway to receive requests for configuration changes, and a pathway to command changes in the different cells or I/O. The combination of the service processor and the micro-controllers support dynamic changes to the partition configuration.

Managing a computer system having a plurality of partitions using a service processor

Methods and apparatus in a partitionable computing system. The system can include a computer readable medium comprising instructions configured to move an element of a first partition to a second partition.

Security measures in a partitionable computing system

A router routes packets among a plurality of nodes based on entries in a route table. Entries in a route table enable mask characterize the enablement of the route table entries. The router receives a packet including an indication to modify the route table enable mask from one of the nodes. The router produces an update mask and determines which logical operation to perform on the update mask and the route table enable mask in response to at least one of the received packet, the update mask, and the route table enable mask. The router generates a new route table enable mask by performing the appropriate logical operation on the update mask and the route table enable mask in response to the determination of which logical operation should be performed and the route table enable mask is replaced with the new route table enable mask.

Enablement of route table entries

Growing community of inventors

Chico, CA, United States of America

Guy Lowell Kuntz