Arm Limited

Zentian Limited

Advanced Risc Machines Limited

Guy Larri

Mark Catchpole

Damian Kelly Harris-Dowsett

Timothy Brian Reynolds

Daren Croxford

Stephan Diestelhorst

Matthew James Horsnell

David Raymond Lutz

Dominic Hugo Symes

David James Seal

David Vivian Jaggar

Miles Robert Dooley

Simon Charles Watt

Alastair David Reid

Mladen Wilder

Lee Douglas Smith

Michael Thomas Kilpatrick

Julian Katenbrink

Todd Rafacz

The present disclosure relates to a method of operating a graphics processing system for providing frames over communication channel in a communication network, the graphics processing system being configured to process data for an application executed thereon to render frames for the application to be output for transmission over the communication channel to a client device, the method comprising: determining network characteristics of the communication network and/or server characteristics of the server; adaptively selecting a first prediction method from a plurality of prediction methods to be used for displaying frames based on the determined network characteristics and/or server characteristics; generating a plurality of frames based on the first prediction method; and selectively providing, based on the first prediction method, one or more output frames from the plurality of frames to the application to be output for transmission over the communication channel.

Graphics processing system

A system includes a fixed-point accumulator for storing numbers in an anchored fixed-point number format, a data interface arranged to receive a plurality of weight values and a plurality of data values represented in a floating-point number format, and logic circuitry. The logic circuitry is configured to: determine an anchor value indicative of a value of a lowest significant bit of the anchored fixed-point number format; convert at least a portion of the plurality of data values to the anchored fixed-point number format; perform MAC operations between the converted at least portion and respective weight values, using fixed-point arithmetic, to generate an accumulation value in the anchored fixed-point number format; and determine an output element of a later of a neural network in dependence on the accumulation value.

Method and apparatus for data processing operation

When a graphics processor is processing data for an application on a host processor, the graphics processor generates in advance of their being required for display by the application a plurality of frame sequences corresponding to a plurality of different possible 'future states' for the application. The graphics processing system, when producing a frame in a sequence of frames corresponding to a given future state for the application, determines one or more region(s) of the frame that are to be produced at a first, higher quality, and producing the determined region(s) of the frame at a first, higher quality, whereas other regions of the frame are produced at a second, lower quality.

Graphics processing systems

A human-machine interface system comprises a sensor configured to generate data associated with a human movement, such as measured electrical signals or data from an accelerometer. A measurement unit of the human-machine interface measures user movement over time to generate a sequence of measured user movement data. A processor processes the data associated with a human movement from the sensor using a trained neural network to determine one or more predicted user actions. A comparison unit compares the one or more predicted user actions with one or more user actions obtained from the sequence of measured user movement data. A control unit uses the predicted user actions to control a process in an information processing apparatus in dependence upon the comparison performed by the comparison unit.

Human-machine interface system

An apparatus () with multiple processing elements () has shared transactional processing resources () for supporting processing of transactions, which comprise operations performed speculatively following a transaction start event whose results are committed following a transaction end event. The transactional processing resources may have a significant overhead and sharing these between the processing elements helps reduce energy consumption and circuit area.

Apparatus with shared transactional processing resource, and data processing method

An acoustic coprocessor is provided. The acoustic coprocessor may include an interface for receiving at least one feature vector and a calculating apparatus for calculating distances indicating the similarity between the at least one feature vector and at least one acoustic state of an acoustic model read from an acoustic model memory. The acoustic coprocessor may also include an interface for sending at least one distance calculated by the calculating apparatus.

Speech recognition circuit and method

An apparatus () has processing circuitry () having access to a first processing resource (-) and a second processing resource (-). A first thread can be processed using the first processing resource. In a thread mode the second processing resource (-) can be used to process a second thread while in a transaction mode the second processing resource (-) can be used to process a transaction of the first thread comprising a number of speculatively performed operations for which results are committed at the end of the transaction. By sharing resources for supporting additional threads and supporting transactions, circuit area and power consumption can be reduced.

Switching between thread mode and transaction mode for a set of registers

A speech recognition circuit comprising a circuit for providing state identifiers which identify states corresponding to nodes or groups of adjacent nodes in a lexical tree, and for providing scores corresponding to said state identifiers, the lexical tree comprising a model of words. The circuit includes: a memory structure for receiving and storing state identifiers identified by a node identifier identifying a node or group of adjacent nodes, the memory structure being adapted to allow lookup to identify particular state identifiers, reading of the scores corresponding to the state identifiers, and writing back of the scores to the memory structure after modification of the scores; an accumulator for receiving score updates corresponding to particular state identifiers from a score update generating circuit which generates the score updates using audio input, for receiving scores from the memory structure, and for modifying said scores by adding said score updates to said scores; and a selector circuit for selecting at least one node or group of adjacent nodes of the lexical tree according to said scores.

Distributed pipelined parallel speech recognition system

A processing apparatus includes floating point arithmetic circuitry coupled to monitoring circuitry. The monitoring circuitry stores exponent limit data indicating at least one of a maximum exponent value and a minimum exponent value processed when performing the floating point arithmetic operations. The monitoring circuitry may be selectively enabled in dependence upon a virtual machine identifier, an application specific identifier or a program counter value range. Exponent limit data may be gathered in respect of different portions of the floating point arithmetic circuitry and/or may be aggregated to form global exponent limit data for the system.

Exponent monitoring

A cache is provided comprising a plurality of ways, each way of the plurality of ways comprising a data array, wherein a data item stored by the cache is stored in the data array of one of the plurality of ways. A way tracker of the cache has a plurality of entries, each entry of the plurality of entries for storing a data item identifier and for storing, in association with the data item identifier, an indication of a selected way of the plurality of ways to indicate that a data item identified by the data item identifier is stored in the selected way. Each entry of the way tracker is further for storing a miss indicator in association with the data item identifier, wherein the miss indicator is set by the cache when a lookup for a data item identified by that data item identifier has resulted in a cache miss. A corresponding method of caching data is also provided.

Tracking the content of a cache using a way tracker having entries with a cache miss indicator

A speech recognition circuit comprising a circuit for providing state identifiers which identify states corresponding to nodes or groups of adjacent nodes in a lexical tree, and for providing scores corresponding to said state identifiers, the lexical tree comprising a model of words; a memory structure for receiving and storing state identifiers identified by a node identifier identifying a node or group of adjacent nodes, said memory structure being adapted to allow lookup to identify particular state identifiers, reading of the scores corresponding to the state identifiers, and writing back of the scores to the memory structure after modification of the scores; an accumulator for receiving score updates corresponding to particular state identifiers from a score update generating circuit which generates the score updates using audio input, for receiving scores from the memory structure, and for modifying said scores by adding said score updates to said scores; and a selector circuit for selecting at least one node or group of adjacent nodes of the lexical tree according to said scores.

A data processing apparatus and method for performing multiply-accumulate operations is provided. The data processing apparatus includes data processing circuitry responsive to control signals to perform data processing operations on at least one input data element. Instruction decoder circuitry is responsive to a predicated multiply-accumulate instruction specifying as input operands a first input data element, a second input data element, and a predicate value, to generate control signals to control the data processing circuitry to perform a multiply-accumulate operation by: multiplying said first input data element and said second input data element to produce a multiplication data element; if the predicate value has a first value, producing a result accumulate data element by adding the multiplication data element to an initial accumulate data element; and if the predicate value has a second value, producing the result accumulate data element by subtracting the multiplication data element from the initial accumulate data element. Such an approach provides a particularly efficient mechanism for performing complex sequences of multiply-add and multiply-subtract operations, facilitating improvements in performance, energy consumption and code density when compared with known prior art techniques.

Apparatus and method for performing multiply-accumulate operations

A speech recognition circuit comprising a circuit for providing state identifiers which identify states corresponding to nodes or groups of adjacent nodes in a lexical tree, and for providing scores corresponding to said state identifiers, the lexical tree comprising a model of words; a memory structure for receiving and storing state identifiers identified by a node identifier identifying a node or group of adjacent nodes, the memory structure being adapted to allow lookup to identify particular state identifiers, reading of the scores corresponding to the state identifiers, and writing back of the scores to the memory structure after modification of the scores; an accumulator for receiving score updates corresponding to particular state identifiers from a score update generating circuit which generates the score updates using audio input, for receiving scores from the memory structure, and for modifying the scores by adding the score updates to the scores; and a selector circuit for selecting at least one node or group of adjacent nodes of the lexical tree according to the scores.

A microprocessor system comprising a register bank,and an execution unit,incorporating a barrel shifter,and an ALU,is provided. The register bank,has X read ports whilst at least some of the program instructions require Y input operands to be read from the register bank,where Y is greater than X. A cache register,is provided that caches previously read input operands for supply to the barrel shifter,and if it is detected that the same register is being read a second or subsequent time then this cached value is supplied to the barrel shifter,rather than requiring a further read from the register bank,A tag register,associated with each cache register,draws data indicating from which register within the register bank,the cached data value was copied. A valid flag,indicates that that cached data value is still current, i.e. at the corresponding register within the register bank,has not been overwritten.

Growing community of inventors

Cambridge, United Kingdom

Guy Larri