International Business Machines Corporation

Globalfoundries Inc.

Guy L Guthrie

William John Starke

Derek E Williams

Ravi Kumar Arimilli

Hugh Shen

Jeffrey A Stuecheli

John Steven Dodson

James Stephen Fields, Jr

Leo James Clark

Phillip G Williams

Sanjeev Ghai

Lakshminarayana Baba Arimilli

Jody B Joyner

Jerry Don Lewis

Michael Steven Siegel

Robert Alan Cargnoni

Bernard Charles Drerup

Hien Le

Geraint M North

Benjiman L Goodman

Bradly George Frey

Cathy May

Naresh Nayar

Charles Francis Marino

John Steve Dodson

Luke Murray

Danny Marvin Neal

Robert H Bell, Jr

Praveen S Reddy

Steven Mark Thurber

Richard Allen Kelley

Jeff A Stuecheli

Vicente Enrique Chung

Philip G Williams

David John Krolak

Kirk Samuel Livingston

Harmony Lynn Helterhoff

Kevin Franklin Reick

Thomas L Jeremiah

John Thomas Hollaway, Jr

Jonathan R Jackson

John David Irish

Stephen J Powell

Paul Allen Ganfield

Charles David Wait

Alvan Wing Ng

David W Cummings

Karthick Rajamani

Malcolm Scott Ware

Richard James Eickemeyer

Bryan J Lloyd

Sheldon Bernard Levenstein

Ronald Nick Kalla

Venkat Rajeev Indukuru

Mohit Karve

Aaron Christoph Sawdey

Kimberly Marie Fernsler

William Lloyd McNeil

Hung Qui Le

Balaram Sinharoy

Brian William Thompto

Michael Stephen Floyd

Eric Eugene Retter

Peter Kenneth Szwed

David Allen Hrusecky

Richard Loise Arndt

Florian Alexander Auernhammer

Gregory Scott Still

Piyush Chunilal Patel

Thomas R Puzak

Bradley Nelson

Robert Allen Drehmel

David A Campbell

Jon K Kriegel

Steven R Kunkel

Wayne Melvin Barrett

George W Rohrbaugh, Iii

Bradley David McCredie

George William Daly, Jr

Frederick Jacob Ziegler

Benjamin Nowak

Jeffrey W Kellington

Ramakrishnan Rajamony

Brian Mitchell Bass

Kenneth Lee Wright

Susan Elizabeth Eisen

Albert James Van Norstrand, Jr

Kenneth Michael Valk

Elizabeth A McGlone

Robert J Blainey

Edward John Silha

Robert Allen Cordes

Gary Dean Anderson

Joseph Gerald McDonald

Richard Nicholas

Ross Boyd Leavens

Dhivya Jeganathan

Randall Ray Heisch

Naga P Gorti

Ronald Xavier Arroyo

A data processing system includes a master, a central request agent, and a plurality of snoopers communicatively coupled to a system fabric for communicating requests subject to retry. The master issues on the system fabric a multicast request intended for the plurality of snoopers. The central request agent receives the multicast request on the system fabric, assigns the multicast request to a particular state machine among a plurality of state machines in the central request agent, and provides the master a coherence response indicating successful completion of the multicast request. The central request agent repetitively issues on the system fabric a multicast request in association with a machine identifier identifying the particular state machine until a coherence response indicates the multicast request is successfully received by all of the plurality of snoopers.

Centralized distribution of multicast requests in a data processing system

A destination host includes a processor core, a system fabric, a memory system, and a link controller communicatively coupled to the system fabric and configured to be communicatively coupled, via a communication link, to a source host with which the destination host is non-coherent. The destination host migrates, via the communication link, a state of a logical partition from the source host to the destination host and page table entries for translating addresses of a dataset of the logical partition from the source host to the destination host. After migrating the state and page table entries, the destination host initiates execution of the logical partition on the processor core while at least a portion of the dataset of the logical partition resides in the memory system of the source host and migrates, via the communication link, the dataset of the logical partition to the memory system of the destination host.

Memory migration within a multi-host data processing environment

A method, programming product, processor, and/or system for prefetching data is disclosed that includes: receiving a request for data at a cache; identifying whether the request for data received at the cache is a demand request or a prefetch request; and determining, in response to identifying that the request for data received at the cache is a prefetch request, whether to terminate the prefetch request, wherein determining whether to terminate the prefetch request comprises: determining how many hits have occurred for a prefetch stream corresponding to the prefetch request received at the cache; and determining, based upon the number of hits that have occurred for the prefetch stream corresponding to the prefetch request received by the cache, whether to terminate the prefetch request.

Prefetch unit filter for microprocessor

In at least some embodiments, a store-type operation is received and buffered within a store queue entry of a store queue associated with a cache memory of a processor core capable of executing multiple simultaneous hardware threads. A thread identifier indicating a particular hardware thread among the multiple hardware threads that issued the store-type operation is recorded. An indication of whether the store queue entry is a most recently allocated store queue entry for buffering store-type operations of the hardware thread is also maintained. While the indication indicates the store queue entry is a most recently allocated store queue entry for buffering store-type operations of the particular hardware thread, the store queue extends a duration of a store gathering window applicable to the store queue entry. For example, the duration may be extended by decreasing a rate at which the store gathering window applicable to the store queue entry ends.

Adjusting store gather window duration in a data processing system supporting simultaneous multithreading

A first instruction for processing by a processor core is received. Whether the instruction is a larx is determined. Responsive to determining the instruction is a larx, whether a cacheline associated with the larx is locked is determined. Responsive to determining the cacheline associated with the larx is not locked, the cacheline associated with the larx is locked and a counter associated with a first thread of the processor core is started. The first thread is processing the first instruction.

Prioritization of threads in a simultaneous multithreading processor core

A coherent data processing system includes a system fabric communicatively coupling a plurality of nodes arranged in a plurality of groups. A plurality of coherence agents are distributed among the nodes and are assigned responsibility for certain addresses. A topology data structure indicates by group and node differing physical locations within the data processing system of the plurality of coherence agents. A master accesses the topology data structure utilizing a request address to obtain a particular group and node of a particular coherence agent uniquely assigned the request address. The master initially issues, on the system fabric, a memory access request specifying the request address and utilizing a remote scope of broadcast that includes the particular node and excludes at least one other node in the particular group, where the particular node is a different one of the plurality of nodes than a home node containing the master.

Broadcast scope selection in a data processing system utilizing a memory topology data structure

A plurality of entries including address translation information are buffered in a data structure in a processor core. At least first and second translation entry invalidation requests specifying different first and second addresses are checked against all of the entries in the data structure. The checking includes accessing and checking at least a first entry in the data structure for an address match with the first address but not the second address, thereafter concurrently checking at least a second entry for an address match with both the first and second addresses, and thereafter completing checking for the first address and accessing and checking the first entry for an address match with the second address but not the first address. The processor core invalidates any entry in the data structure for which the checking detects an address match.

Concurrent processing of translation entry invalidation requests in a processor core

An arbiter gathers translation invalidation requests assigned to state machines of a lower-level cache into a set for joint handling in a processor core. The gathering includes selection of one of the set of gathered translation invalidation requests as an end-of-sequence (EOS) request. The arbiter issues to the processor core a sequence of the gathered translation invalidation requests terminating with the EOS request. Based on receipt of each of the gathered requests, the processor core invalidates any translation entries providing translation for the addresses specified by the translation invalidation requests and marks memory-referent requests dependent on the invalidated translation entries. Based on receipt of the EOS request and in response to all of the marked memory-referent requests draining from the processor core, the processor core issues a completion request to the lower-level cache indicating completion of servicing by the processor core of the set of gathered translation invalidation requests.

Gathering translation entry invalidation requests in a data processing system

A processing unit includes a processor core and an associated cache memory. The cache memory establishes a reservation of a hardware thread of the processor core for a store target address and services a store-conditional request of the processor core by conditionally updating the shared memory with store data based on the whether the hardware thread has a reservation for the store target address. The cache memory receives a hint associated with the store-conditional request indicating an intent of the store-conditional request. The cache memory protects the store target address against access by any conflicting memory access request during a protection window extension following servicing of the store-conditional request. The cache memory establishes a first duration for the protection window extension based on the hint having a first value and establishes a different second duration for the protection window extension based on the hint having a different second value.

Variable protection window extension for a target address of a store-conditional request

The present disclosure may include a processor that uses idle caches as a backing store for a boot code. The processor designates a boot core and an active cache from a plurality of cores and a plurality of caches. The processor configures remaining caches from the plurality of caches to act as a backing store memory. The processor modifies the active cache to convert cast outs to a system memory into lateral cast outs to the backing store memory. The processor copies a boot image to the backing store memory and executes the boot image by the boot core.

Using idle caches as a backing store for boot code

A multiprocessor data processing system includes multiple vertical cache hierarchies supporting a plurality of processor cores, a system memory, and an interconnect fabric coupled to the system memory and the multiple vertical cache hierarchies. Based on a request of a requesting processor core among the plurality of processor cores, a master in the multiprocessor data processing system issues, via the interconnect fabric, a read-type memory access request. The master receives via the interconnect fabric at least one beat of conditional data issued speculatively on the interconnect fabric by a controller of the system memory prior to receipt by the controller of a systemwide coherence response for the read-type memory access request. The master forwards the at least one beat of conditional data to the requesting processor core.

Speculative delivery of data from a lower level of a memory hierarchy in a data processing system

A coherent data processing system includes a system fabric communicatively coupling a plurality of coherence participants and fabric control logic. The fabric control logic quantifies congestion on the system fabric based on coherence messages associated with commands issued on the system fabric. Based on the congestion on the system fabric, the fabric control logic determines a rate of request issuance applicable to a set of coherence participants among the plurality of coherence participants. The fabric control logic issues at least one rate command to set a rate of request issuance to the system fabric of the set of coherence participants.

Controlling issue rates of requests of varying broadcast scopes in a data processing system

A data processing system includes a plurality of processor cores each supported by a respective one of a plurality of vertical cache hierarchies. Based on receiving on a system fabric a cache injection request requesting injection of a data into a cache line identified by a target real address, the data is written into a cache in a first vertical cache hierarchy among the plurality of vertical cache hierarchies. Based on a value in a field of the cache injection request, a distribute field is set in a directory entry of the first vertical cache hierarchy. Upon eviction of the cache line the first vertical cache hierarchy, a determination is made whether the distribute field is set. Based on determining the distribute field is set, a lateral castout of the cache line from the first vertical cache hierarchy to a second vertical cache hierarchy is performed.

Distribution of injected data among caches of a data processing system

A data processing system includes system memory and a plurality of processor cores each supported by a respective one of a plurality of vertical cache hierarchies. A first vertical cache hierarchy records information indicating communication of cache lines between the first vertical cache hierarchy and others of the plurality of vertical cache hierarchies. Based on selection of a victim cache line for eviction, the first vertical cache hierarchy determines, based on the recorded information, whether to perform a lateral castout of the victim cache line to another of the plurality of vertical cache hierarchies rather than to system memory and selects, based on the recorded information, a second vertical cache hierarchy among the plurality of vertical cache hierarchies as a recipient of the victim cache line via a lateral castout. Based on the determination, the first vertical cache hierarchy performs a castout of the victim cache line.

Targeting of lateral castouts in a data processing system

A data processing system includes a plurality of snoopers, a processing unit including master, and a system fabric communicatively coupling the master and the plurality of snoopers. The master sets a retry operating mode for an interconnect operation in one of alternative first and second operating modes. The first operating mode is associated with a first type of snooper, and the second operating mode is associated with a different second type of snooper. The master issues a memory access request of the interconnect operation on the system fabric of the data processing system. Based on receipt of a combined response representing a systemwide coherence response to the request, the master delays an interval having a duration dependent on the retry operating mode and thereafter reissues the memory access request on the system fabric.

Data processing system having masters that adapt to agents with differing retry behaviors

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Austin, TX, United States of America

Guy L Guthrie