Lsi Logic Corporation

Lsi Corporation

Guy Kendall

Brad D Besmer

Stephen B Johnson

Timothy E Hoglund

Brian A Day

Paul Jeffrey Smith

Christopher McCarty

Andrew Carl Brown

Bradley Dean Besmer

Roger T J Clegg

An apparatus and method to allocate memory in a storage system. Firmware running the method uses an iterative approach to find the best optimal memory configuration for a particular storage system given a variety of configuration data parameters stored as persistent data in non-volatile flash memory. The configuration data relates to resources in the environment that the storage system is found in, such as the number of virtual ports, targets and initiators supported by a storage system IOC. The configuration data is alterable, to allow flexibility in updating and changing parameters, and is employed at runtime when the storage system powers on, to enable the most flexible resource allocation. In a preferred method of determining the most optimal memory configuration for a given set of parameters corresponding to a given set of resources, an iterative method is employed to decrement parameter values from their maximum values, taking into account the minimums, and then testing the configuration by performing a memory allocation. If the allocation fails, because for example the wrong type memory or size of memory for any of the resources found, then the firmware resets the memory areas back to predetermined Start of Day (SOD) parameter values, decrements the values until a successful configuration of memory is found for the given set of parameters, and tries again, or until the firmware is caused to fault, whichever comes first.

System and method for optimal dynamic resource allocation in a storage system

Circuits and associated methods for testing internal operation of an application integrated circuit. Features and aspects hereof add configurable test interrupt circuits to an application circuit design to permit dynamic, configurable interrupt generation from an integrated circuit based on conditions determined from monitoring of internal signals of the application circuit. The internal signals that may be tested and used to generate test interrupts are those not exposed to the external processor interface of the integrated circuit and thus may be configured to interrupt based on any internal state of the application specific functional circuits of the integrated circuit.

Circuits and associated methods for improved debug and test of an application integrated circuit

In a computer system, a bus adapter processes bus operation information structures for performing bus operations by automatically starting processing each bus operation information structure after completing processing the previous bus operation information structure. A processor forms the bus operation information structures and sets control over each bus operation information structure to a sequencer for processing. When a next bus operation information structure is ready for processing after completing processing the previous bus operation information structure, the sequencer checks whether it has control over the next bus operation information structure, and if so, begins processing the next bus operation information structure without being instructed to do so by the processor.

Bus sequence operation with automatic linking from current I/O information to subsequent I/O information

An apparatus comprising a plurality of IO queues and a logic circuit. The plurality of IO queues each may be configured to receive a respective IO request and present the IO request in response to a trigger signal. The logic circuit may be configured to (a) (i) receive one or more of the IO requests and (ii) serially coalesce the IO requests in response to a respective device identification (ID) of the IO requests, and (iii) present one or more of the coalesced IO requests as one or more respective context queue requests in response to the trigger signal and (b) generate the trigger signal when a current queue count is equal to a maximum queue depth.

Method and/or apparatus to sort request commands for SCSI multi-command packets

A message-based I/O architecture comprising a list describing one or more source buffers and a message header. The list may be segmented in multiple memory locations. The message header may be configured to (i) indicate whether the list is segmented and (ii) provide information for linking the list when the list is segmented.

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Colorado Springs, CO, United States of America

Guy Kendall