Marvell International Limited

Cavium, Inc.

Marvell Asia Pte., Ltd.

Marvellworld Trade Ltd.

Synaptics Corporation

Cisco Technology, Inc.

Arm Limited

Cavium International

Guy Hutchison

Gerald Schmidt

Awais Bin Nemat

Martin Leslie White

Harish Krishnamoorthy

Vishal Anand

Zubin Shah

Sachin Ramesh Gandhi

Tsahi Daniel

Albert Fishman

Weihuang Wang

Raghu R Kondapalli

Kamal Dalmia

Saurabh Shrivastava

Premshanth Theivendran

Ben Chen

Dan Tu

David William Steer

Prasanna Vetrivel

A software-defined network (SDN) system, device and method comprise one or more input ports, a programmable parser, a plurality of programmable lookup and decision engines (LDEs), programmable lookup memories, programmable counters, a programmable rewrite block and one or more output ports. The programmability of the parser, LDEs, lookup memories, counters and rewrite block enable a user to customize each microchip within the system to particular packet environments, data analysis needs, packet processing functions, and other functions as desired. Further, the same microchip is able to be reprogrammed for other purposes and/or optimizations dynamically.

Protocol independent programmable switch (PIPS) for software defined data center networks

A new approach of systems and methods to support a hierarchical interrupt propagation scheme for efficient interrupt propagation and handling is proposed. The hierarchical interrupt propagation scheme organizes a plurality of slave interrupt handlers associated functional blocks in a chip in a hierarchy. When an exception or error condition occurs in a functional block, a slave interrupt handler associated with the functional block creates an interrupt packet as an interrupt notification and utilizes pre-existing input and output interfaces that have already been utilized for accessing registers of the functional block to transmit the created interrupt packet to a central interrupt handler through the hierarchy without running dedicated interconnect wires out of the functional block. The central interrupt handler then processes the interrupt notifications and provides a response packet to the interrupt notification back to slave interrupt handler that created the interrupt packet to configure or adjust the functional block accordingly.

System and methods for hierarchical inline interrupt scheme for efficient interrupt propagation and handling

A method and system for securing CSI and DSI links using enhanced authentication and cloud tracking are disclosed. According to one embodiment, a method comprises receiving at the receiving device an encrypted information signal from the transmitting device. The encrypted information signal includes a unique identifier of the transmitting device. The method further comprises testing whether a whitelist at the receiving device includes the unique identifier of the transmitting device. The encrypted information signal is decrypted producing a retrieved information signal only if the whitelist includes the unique identifier of the transmitting device; and otherwise terminating communication with the transmitting device.

Method and system for securing communication links using enhanced authentication

A method and system for securing in-vehicle ethernet links are disclosed. According to one embodiment, a method comprises receiving from an authenticator, via an insecure channel, a public key of the authenticator, a random number, and a challenge. A private key of the peer that was supplied to the peer is accessed from local storage at the peer. A state machine computes a session key for the peer, based on the random number, the public key of the authenticator, and the private key of the peer. The state machine computes a peer response to the challenge using the session key for the peer and a symmetric cipher function.

Method and system for securing in-vehicle ethernet links

Systems and methods for generating an RTL description based on logical signal groupings are described. Logical interfaces are declared in a compressed form, and logical signal grouping is defined in a markup document. The definitions from the markup document are used by expansion scripts to populate RTL modules and encapsulate block connectivity and functionality. Multiple interfaces can be created instantly, and interface definitions for common interfaces may be easily re-defined. Default values may be assigned to module outputs for testing purposes, allowing for multi-module simulations where certain modules are shelled-out.

Approach for logic signal grouping and RTL generation using XML

An error detection circuit on a semiconductor chip detects whether soft errors have affected flip-flop implemented registers on the semiconductor chip. A signature of these flip-flop implemented registers on the semiconductor chip is periodically captured. The signature allows for the integrity of the flip-flop implemented registers to be constantly monitored. A soft error occurring on any of the flip-flop implemented registers can be immediately detected. In response to the detection, an interrupt is raised to notify software to take action.

Apparatus and a method of detecting errors on registers

Embodiments of the present invention are directed to a configuration interface of a network ASIC. The configuration interface allows for two modes of traversal of nodes. The nodes form one or more chains. Each chain is in a ring or a list topology. A master receives external access transactions. Once received by the master, an external access transaction traverses the chains to reach a target node. A target node either is an access to a memory space or is a module. A chain can include at least one decoder. A decoder includes logic that determines which of its leaves to send an external access transaction to. In contrast, if a module is not the target node, then the module passes an external access transaction to the next node coupled thereto; otherwise, if the module is the target node, the transmission of the external access transaction stops at the module.

Method of implementing a network ASIC in a network device

Embodiments of the present invention are directed to a multiple-interrupt propagation scheme, which is an automated mechanism for the specification and creation of interrupts. Interrupts originating at leaf nodes of a network chip are categorized into different service levels according to their interrupt types and are propagated to a master of the network chip via a manager. For each interrupt, depending on its service level, the manager either instantaneously propagates the interrupt or delays propagation of the interrupt to the master. The master forwards the interrupts to different destinations. A destination can be a processing element that is located on the network chip or externally on a different chip.

Multiple-interrupt propagation scheme in a network ASIC

Two modes of a configuration interface of a network ASIC

An on-chip crossbar of a network switch comprising a central arbitration component configured to allocate packet data requests received from destination port groups to memory banks. The on-chip crossbar further comprises a Benes routing network comprising a forward network having a plurality of pipelined forward routing stages and a reverse network, wherein the Benes routing network retrieves the packet data from the memory banks coupled to input of the Benes routing network and route the packet data to the port groups coupled to output of the Benes routing network. The on-chip crossbar further comprises a plurality of stage routing control units each associated with one of the forward routing stages and configured to generate and provide a plurality of node control signals to control routing of the packet data through the forward routing stages to avoid contention between the packet data retrieved from different memory banks at the same time.

Apparatus and method for on-chip crossbar design in a network switch using benes network

Protocol independent programmable switch (PIPS) software defined data center networks

A new approach is proposed that contemplates systems and methods to support automatic timing adjustment of a plurality of paths carrying metadata of incoming data packets in a network switch to meet their respective timing constraints. First, the paths for transmitting different pieces of metadata of incoming packets are identified in the network switch. Once the metadata paths are identified, the proposed approach identifies the timing constraints that the metadata paths need to satisfy in order for the network switch to function properly. The proposed approach then calculates the current delays of the metadata paths and determines optimal timing values of each of the metadata paths in order to meet the timing constraints. The optimal timing values of the metadata paths are then compared to the current delays of the metadata paths to identify the paths which current delay values need to be adjusted. These identified metadata paths are then adjusted accordingly to meet the timing constraints at the minimum cost in terms of additional areas taken by devices and interconnect wires need to be included in the layout of the network switch.

Systems and methods for timing adjustment of metadata paths in a network switch under timing constraints

A multiple access mechanism allows sources to simultaneously access different target registers at the same time without using a semaphore. The multiple access mechanism is implemented using N holding registers and source identifiers. The N holding registers are located in each slave engine. Each of the N holding registers is associated with a source and is configured to receive partial updates from the source before pushing the full update to a target register. After the source is finished updating the holding register and the holding register is ready to commit to the target register, a source identifier is added to a register bus. The source identifier identifies the holding register as the originator of the transaction on the register bus. The N holding registers are able to simultaneously handle N register transactions. The max value of N is 2, where n is the number of bits in the source identifier.

Growing community of inventors

Santa Clara, CA, United States of America

Guy Hutchison