Agilent Technologies, Inc.

Hewlett-Packard Company

Avago Technologies General IP (Singapore) Pte. Ltd.

Avago Technologies General IP Pte, Ltd.

Guy Harlan Humphrey

David Lawrence Linam

Richard Alan Krzyzkowski

C Stephen Dondale

Laurent F Pinot

Jeffrey R Rearick

Gayvin E Stong

Paul Douglas Nuber

Scott T Evans

Manuel Salcido

Gilbert Yoh

M Jason Welch

Gerald L Esch, Jr

Jason Gonzalez

Gerald John D'Amato

Christopher George Helt

Dan Stotz

Salvador Salcido

Edgardo Pablo Lopez

Kristin Marie Richling

Michael Jason Welch

Stephen E Clarke

Jerry D'Amato

Rory L Fisher

Richard A Krzyzlowski

Preamble release training in a double data-rate dynamic random access memory interface uses feedback from read operations to adjust the preamble release signal so that the preamble release signal continues to be activated close to the middle of the preamble. A first signal, and then a second signal, are generated in response to an initiation of a read operation. The first and second signals are characterized by a delay from the initiation of the read operation of one or more clock cycles plus a fine delay contributed by an adjustable delay circuit. The first signal is provided to a data strobe parking circuit that uses it to release or un-park the data strobe signal lines. The second signal is phase-compared with the data strobe signal associated with incoming data during the read operation. The adjustable delay circuit is adjusted in response to the result of the comparison.

Continuous tuning of preamble release timing in a double data-rate memory device interface

A method and apparatus for testing an integrated circuit interconnect comprises an IC having circuitry embedded in the IC capable of providing a pseudo time domain reflectometry test by launching a test transition onto the interconnect and capturing a reflection of the test transition.

Method and apparatus for an embedded time domain reflectometry test

A hybrid binary/thermometer code is employed to adjust the output impedance of a variable impedance output driver circuit having an impedance network comprising a plurality of impedance legs each programmably electrically connectable according to the hybrid binary/thermometer code in parallel between a voltage source and the signal pad. The plurality of impedance legs are partitioned into one or more set pairs of binary stepped impedance legs and corresponding thermometer stepped impedance legs. A binary set of calibration signals in the hybrid binary/thermometer code steps a given set of binary stepped impedance legs according to a binary code and a thermometer set of calibration signals in the hybrid binary/thermometer code steps the corresponding set of thermometer stepped impedance legs according to a thermometer code once per full count iteration of the binary set of calibration signals.

Hybrid binary/thermometer code for controlled-voltage integrated circuit output drivers

A second single-ended receiver having a first stage for receiving an input signal and outputting a pair of corresponding output signals, and a second stage for receiving the pair of output signals and outputting a corresponding single output signal. First and second pull-down transistors are coupled to first and second inputs to the first stage. A bias circuit electrically biases the first stage, second stage, and first and second pull-down transistors, and a power supply provides power to those components.

Stable process induced correction bias circuitry for receivers on single-ended applications

A novel method and apparatus is presented for reducing the slew rate of transition edges of a digital signal on a node of an integrated circuit by connecting transistors with differing threshold voltages between the node and a voltage source and driving the gates of these transistors with the same driving signal.

Slew rate control of output drivers using FETs with different threshold voltages

An electrostatic discharge (ESD) structure for use in an integrated circuit (IC). The ESD structure comprises a metallic resistor and a metallic capacitor that are electrically coupled in series to form a resistor-capacitor (RC) component having an appropriate RC time constant. The RC component maintains a level of charge between ground and a shunt node to ensure that, during an ESD event, electrostatic charge on a power supply, VDD, associated with the ESD structure is shunted via a shunt path from said power supply VDD to said ground. By using metal to create the metal resistor and capacitor, charge leakage problems that result from parasitic capacitance associated with using an RC component comprised of either a poly, active, or nwell resistor in combination a diode are eliminated. By eliminating such charge leakage problems, a more reliable RC component, and thus a more reliable RC time constant, are obtained.

Method and apparatus for creating a reliable long RC time constant

A pad driver method and apparatus is presented. The pad driver includes a dual path configuration. The dual path includes a first path and a second path. Both paths include a pre-driver. The first path and the second path communicate high voltage signals and low voltage signals. The pre-driver in the first path drives a pFET device. The pre-driver in the second path drives an nFET device. The pFET and nFET devices provide an output signal, which drives a pad. Each pre-driver further includes a first path and a second path. The first path in the pre-driver supports high voltage operation and the second path in the pre-driver supports low voltage operation.

Programmable driver method and apparatus for high and low voltage operation

A system for simplifying clock construction and distribution within an integrated circuit, and for simplifying analysis within the integrated circuit. The system utilizes a memory, software stored within said memory defining functions to be performed by the system, and a processor. The processor is configured by the software to: read a defined location for a clock generator within the integrated circuit, wherein the clock generator generates a clock signal; read a defined number of interconnect routes to be created within the integrated circuit, wherein a subset of the number of interconnect routes corresponds to a number of logical blocks that will later be provided within the integrated circuit, and wherein each of the interconnect routes within the subset comprises an open end for one of the logical blocks to be placed; test electrical characteristics and functionality of the integrated circuit to ensure that a time for the clock signal to traverse each of the interconnect routes within the subset is equal, and change properties within the integrated circuit if the clock signal traversal time is not equal; and add the logical blocks to each of the interconnect routes within the subset, wherein each of the logical blocks is connected to the open end of one of the interconnect routes within the subset.

System and method for simplifying clock construction and analysis

A method and circuit for controlling the slope of a transitioning signal on a transmission line of integrated circuit is achieved using stepwise pull-down impedance reduction/augmentation. Over a series of sequentially ordered steps, a predetermined decreasing (or increasing) impedance is connected between the transmission line and voltage source. Using certain predetermined impedance values in order, a linear slew rate on the output signal is achievable. Adjusting the time delay between each step allows the slope of the linear slew rate to be adjusted.

Variable slew rate control for open drain bus

A novel method and apparatus is presented for reducing the slew rate of transition edges of a digital signal on a node of an integrated circuit by adjusting the source resistance of the pre-drive devices to generate a slew-controlled pre-drive signal for driving the output drive devices.

Slew rate control of output drivers using PVT controlled edge rates and delays

A technique for preventing high current shorts through I/O pads of an integrated circuit during power up and power down is presented. In accordance with the invention, the voltage levels of the core power supply that powers the internal circuitry of the integrated circuit and the I/O power supply that powers the input and/or output pad drivers is monitored to detect the condition wherein the core power supply is powered down and the I/O power supply is powered up. Upon detection of this condition, the pad drivers are disabled, preferably by disabling the pre-drivers that generate the pre-drive signals that drive the output driver devices. In a preferred embodiment, the process/voltage/temperature adjustment circuitry is leveraged to disable the output pads during power up and down.

Method for reducing short circuit current during power up and power down for high voltage pad drivers with analog slew rate control

The present disclosure relates to a contact arrangement. The contact arrangement comprises a plurality of contacts formed along a line in a staggered configuration. The staggered configuration arranges the contacts so as to be diagonally spaced from each other along the line such that the contacts have an effective spacing along the line that is smaller than the actual spacing of the contacts. In one embodiment, the contact arrangement is used to construct an integrated circuit chip assembly that comprises a substrate having a die that is provided with a plurality of signal lines and power lines formed on its surface, the signal lines each including a plurality of signal contacts and signal contacts of at least one signal line are arranged in a staggered configuration so as to be diagonally spaced from each other along the at least one signal line such that the signal contacts have an effective spacing along the at least one signal line that is smaller than the actual spacing of the signal contacts of the at least one signal line.

High density contact arrangement

An electronic circuit and method for processing a signal, including a variable-delay transmission gate for receiving a binary input signal and propagating a delayed binary output signal corresponding to the input signal. The propagation delay in the transmission gate is controlled by two complimentary, non-binary, control signals from a current mirror that is driven by a PVT-compensated voltage follower.

Variable delay CMOS circuit with PVT control

A binary weighted thermometer code is employed to adjust the output impedance of a variable impedance output driver circuit. The driver circuit includes an impedance network comprising a plurality of resistive devices each programmably electrically connectable in parallel between a first voltage source and the signal pad. The resistive devices are partitioned into a plurality of sets. A first set of the resistive devices may be programmed in a binary incremental manner to electrically connect one or more of the resistive devices in the first set between the first voltage source and the signal pad. Only if all of the resistive devices in the first set are activated may a second set of the resistive devices be programmed in a binary incremental manner. Additional sets of the resistive devices may be likewise programmed only after all of the resistive devices in the previously programmed sets are activated.

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Ft. Collins, CO, United States of America

Guy Harlan Humphrey