International Business Machines Corporation

Guy G Tracy

Michael Andrew Blake

Robert J Sonnelitter, Iii

Kenneth Douglas Klapproth

Pak-kin Mak

Ekaterina M Ambroladze

Deanna P D Berger

Chad G Wilson

Timothy Carl Bronson

Deanna Postles Dunn Berger

Ashraf ElSharif

Gregory William Alexander

Craig Raymond Walters

Vesselina K Papazova

Mark R Hodges

Ram Sai Manoj Bamdhamravuri

Arthur J O'Neill

Gary E Strait

Deanna P Berger

Jason D Kohl

Tim Bronson

Richard Joseph Branciforte

Lior Binyamini

Poornima P Sulibele

Timothy W Steele

A computer-implemented method for cache governance includes receiving, at a local cache of a processor chip, a first fetch request for data for a cache line of the local cache. The method further includes allocating a first cache controller to allow the first fetch request to receive the data and to track reception of the data. The method further includes receiving, at the local cache of the processor chip, a second fetch request for the data for the cache line of the local cache. The method further includes determining via an address compare logic associated with the local cache whether the first fetch request in the first cache controller is for a same cache line that the second fetch request is targeting. The method further includes allowing the second fetch request to allocate a second cache controller and copying metadata from the first cache controller to the second cache controller.

Cache governance in a computing environment with multiple processors

A method and a computer system for core recovery management are provided. A first operation signal is generated via a first hardware agent. The first operation signal indicates that the first hardware agent is processing an operation requested by a first processor core. The first processor core receives a first extend fence signal based on the generated first operation signal. As long as the first extend fence signal is received via the first processor core, the first processor core is kept in a fenced state for core recovery.

Preventing extraneous messages when exiting core recovery

Methods, systems and computer program products for measuring hardware performance are provided. Aspects include receiving an indication of a start to a hardware operation. A number of clock cycles are counted from the start of a hardware operation to the completion of the hardware operation. A first region comprising a first set of bit location is defined. A second and third region is defined each including a set of bit locations. Based on the first set of bit locations being equal to zero, a granularity flag is set to zero in the sample buffer and the second and third set of bit locations are written to the sample buffer. And based on the first set of bit locations being greater than zero, the granularity flag in the sample buffer is set to one and the first and second set of bit locations are written to the sample buffer.

Accuracy sensitive performance counters

Processing simultaneous data requests regardless of active request in the same addressable index of a cache. In response to the cache miss in the given congruence, if the number of other compartments in the given congruence class that have an active operation is less than a predetermined threshold, setting a Do Not Cast Out (DNCO) pending indication for each of the compartments that have an active operation in order to block access to each of the other compartments that have active operations and, if the number of other compartments in the given congruence class that have an active operation is not less than a predetermined threshold, blocking another cache miss from occurring in the compartments of the given congruence class by setting a congruence class block pending indication for the given congruence class in order to block access to each of the other compartments of the given congruence class.

Coherent cache with simultaneous data requests in same addressable index

In an approach for purging an address range from a cache, a processor quiesces a computing system. Cache logic issues a command to purge a section of a cache to higher level memory, wherein the command comprises a starting storage address and a range of storage addresses to be purged. Responsive to each cache of the computing system activating the command, cache logic ends the quiesce of the computing system. Subsequent to ending the quiesce of the computing system, Cache logic purges storage addresses from the cache, based on the command, to the higher level memory.

Non-disruptive clearing of varying address ranges from cache

Embodiments of the present invention are directed to a computer-implemented method for ownership tracking updates across multiple simultaneous operations. A non-limiting example of the computer-implemented method includes receiving, by a cache directory control circuit, a message to update a cache directory entry. The method further includes, in response, updating, by the cache directory control circuit, the cache directory entry, and generating a reverse compare signal including an updated ownership vector of a memory line corresponding to the cache directory entry. The method further includes sending the reverse compare signal to a cache controller associated with the cache directory entry.

Ownership tracking updates across multiple simultaneous operations

An aspect includes interlocking operations in an address-sliced cache system. A computer-implemented method includes determining whether a dynamic memory relocation operation is in process in the address-sliced cache system. Based on determining that the dynamic memory relocation operation is in process, a key operation is serialized to maintain a sequenced order of completion of the key operation across a plurality of slices and pipes in the address-sliced cache system. Based on determining that the dynamic memory relocation operation is not in process, a plurality of key operation requests is allowed to launch across two or more of the slices and pipes in parallel in the address-sliced cache system while ensuring that only one instance of the key operations is in process across all of the slices and pipes at a same time.

Operation interlocking in an address-sliced cache system

A computer implemented method for avoiding false activation of hang avoidance mechanisms of a system is provided. The computer implemented method includes receiving, by a nest of the system, rejects from a processor core of the system. The rejects are issued based on a cache line being locked by the processor core. The computer implemented method includes accumulating the rejects by the nest. The computer implemented method includes determining, by the nest, when an amount of the rejects accumulated by the nest has met or exceeded a programmable threshold. The computer implemented method also includes triggering, by the nest, a global reset to counters of the hang avoidance mechanisms of a system in response to the amount meeting or exceeding the programmable threshold.

Deadlock avoidance in a multi-processor computer system with extended cache line locking

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Austin, TX, United States of America

Guy G Tracy